Fast and Accurate Transaction-Level Model of a Wormhole Network-on-Chip with Priority Preemptive Virtual Channel Arbitration

L. S. Indrusiak; O. M. Santos

doi:10.1109/DATE.2011.5763179

Fast and Accurate Transaction-Level Model of a Wormhole Network-on-Chip with Priority Preemptive Virtual Channel Arbitration

L. S. Indrusiak, O. M. Santos

Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Simulation is a bottleneck in the design flow of on-chip multiprocessors. This paper addresses that problem by reducing the simulation time of complex on-chip interconnects through transaction-level modelling (TLM). A particular on-chip interconnect architecture was chosen, namely a wormhole network-on-chip with priority preemptive virtual channel arbitration, because its mechanisms can be modelled at transaction level in such a way that accurate figures for communication latency can be obtained with less simulation time than a cycle-accurate model. The proposed model produced latency figures with more than 90% accuracy and simulated more than 1000 times faster than a cycle-accurate model.

Original language	English
Title of host publication	Design Automation and Test in Europe (DATE), 2011
Pages	1089-1094
Number of pages	6
ISBN (Electronic)	978-3-9810801-7-9
DOIs	https://doi.org/10.1109/DATE.2011.5763179
Publication status	Published - 2011
Event	Design Automation and Test in Europe (DATE 2011) - Grenoble, France Duration: 14 Mar 2011 → 17 Mar 2011

Conference

Conference	Design Automation and Test in Europe (DATE 2011)
Country/Territory	France
City	Grenoble
Period	14/03/11 → 17/03/11

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10.1109/DATE.2011.5763179

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title = "Fast and Accurate Transaction-Level Model of a Wormhole Network-on-Chip with Priority Preemptive Virtual Channel Arbitration",

abstract = "Simulation is a bottleneck in the design flow of on-chip multiprocessors. This paper addresses that problem by reducing the simulation time of complex on-chip interconnects through transaction-level modelling (TLM). A particular on-chip interconnect architecture was chosen, namely a wormhole network-on-chip with priority preemptive virtual channel arbitration, because its mechanisms can be modelled at transaction level in such a way that accurate figures for communication latency can be obtained with less simulation time than a cycle-accurate model. The proposed model produced latency figures with more than 90% accuracy and simulated more than 1000 times faster than a cycle-accurate model.",

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N2 - Simulation is a bottleneck in the design flow of on-chip multiprocessors. This paper addresses that problem by reducing the simulation time of complex on-chip interconnects through transaction-level modelling (TLM). A particular on-chip interconnect architecture was chosen, namely a wormhole network-on-chip with priority preemptive virtual channel arbitration, because its mechanisms can be modelled at transaction level in such a way that accurate figures for communication latency can be obtained with less simulation time than a cycle-accurate model. The proposed model produced latency figures with more than 90% accuracy and simulated more than 1000 times faster than a cycle-accurate model.

AB - Simulation is a bottleneck in the design flow of on-chip multiprocessors. This paper addresses that problem by reducing the simulation time of complex on-chip interconnects through transaction-level modelling (TLM). A particular on-chip interconnect architecture was chosen, namely a wormhole network-on-chip with priority preemptive virtual channel arbitration, because its mechanisms can be modelled at transaction level in such a way that accurate figures for communication latency can be obtained with less simulation time than a cycle-accurate model. The proposed model produced latency figures with more than 90% accuracy and simulated more than 1000 times faster than a cycle-accurate model.

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DO - 10.1109/DATE.2011.5763179

M3 - Conference contribution

SN - 978-1-61284-208-0

SP - 1089

EP - 1094

BT - Design Automation and Test in Europe (DATE), 2011

T2 - Design Automation and Test in Europe (DATE 2011)

Y2 - 14 March 2011 through 17 March 2011

ER -

Fast and Accurate Transaction-Level Model of a Wormhole Network-on-Chip with Priority Preemptive Virtual Channel Arbitration

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