Fast simulation of networks-on-chip with priority-preemptive arbitration

Leandro Soares Indrusiak*, James Harbin, Osmar Marchi Dos Santos

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


An increasingly time-consuming part of the design flow of on-chip multiprocessors is the simulation of the interconnect architecture. The accurate simulation of state-of-the art network-on-chip interconnects can take hours, and this process is repeated for each design iteration because it provides valuable insights on communication latencies that can greatly affect the overall performance of the system. In this article, we identify a time-predictable network-on-chip architecture and show that its timing behaviour can be predicted using models which are far less complex than the architecture itself. We then explore such a feature to produce simplified and lightweight simulation models that can produce latency figures with more than 90% accuracy and simulate more than 1,000 times faster when compared to a cycle-accurate model of the same interconnect.

Original languageEnglish
Article number56
Pages (from-to)1-22
Number of pages22
JournalACM Transactions on Design Automation of Electronic Systems
Issue number4
Publication statusPublished - Sept 2015

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  • Network-on-chip
  • Transaction-level simulation

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