Fast simulation of networks-on-chip with priority-preemptive arbitration

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JournalACM Transactions on Design Automation of Electronic Systems
DatePublished - Sep 2015
Issue number4
Volume20
Number of pages22
Pages (from-to)1-22
Original languageEnglish

Abstract

An increasingly time-consuming part of the design flow of on-chip multiprocessors is the simulation of the interconnect architecture. The accurate simulation of state-of-the art network-on-chip interconnects can take hours, and this process is repeated for each design iteration because it provides valuable insights on communication latencies that can greatly affect the overall performance of the system. In this article, we identify a time-predictable network-on-chip architecture and show that its timing behaviour can be predicted using models which are far less complex than the architecture itself. We then explore such a feature to produce simplified and lightweight simulation models that can produce latency figures with more than 90% accuracy and simulate more than 1,000 times faster when compared to a cycle-accurate model of the same interconnect.

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© 2015 Authors. Publication rights licensed to ACM. This is an author-produced version of the published paper. Uploaded in accordance with the publisher’s self-archiving policy. Further copying may not be permitted; contact the publisher for details

    Research areas

  • Network-on-chip, Transaction-level simulation

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