Fault Attack on AES via Hardware Trojan Insertion by Dynamic Partial Reconfiguration of FPGA over Ethernet

Anju P. Johnson; Sayandeep Saha; Rajat Subhra  Chakraborty; Debdeep Mukhopadhyay; Sezer   Gören

Fault Attack on AES via Hardware Trojan Insertion by Dynamic Partial Reconfiguration of FPGA over Ethernet

Anju P. Johnson, Sayandeep Saha, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay, Sezer Gören

Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We describe a novel methodology to exploit the widely used Dynamic Partial Reconfiguration (DPR) support in Field Programmable Gate Arrays (FPGAs) to implant a hardware Trojan in an Advanced Encryption Standard (AES) encryption
circuit implemented on a FPGA. The DPR is performed by transferring the required partial configuration bitstream file over an Ethernet connection to the FPGA board, from an attacker’s computer which can communicate with the FPGA
over a network. The inserted Trojan launches a “fault attack” on the AES encryption circuit, which enables recovery of the secret key by standard mathematical analysis of the faulty ciphertext produced. To the best of our knowledge, this is the first reported attack which exploits DPR to break
an AES hardware implementation on FPGA. Our implementation results establish this to be an extremely potent attack on AES at low hardware and computational overhead, while using the standard unlicensed FPGA design tools.

Original language	English
Title of host publication	Workshop on Embedded Systems Security (WESS, part of ACM ESWEEK) 2014, New Delhi, India
Publisher	ACM
ISBN (Print)	9781450329323
Publication status	Published - Oct 2014

Keywords

Hardware Trojan
FPGA
Dynamic Partial Reconfiguration
AES
Fault Attack

Cite this

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title = "Fault Attack on AES via Hardware Trojan Insertion by Dynamic Partial Reconfiguration of FPGA over Ethernet",

abstract = "We describe a novel methodology to exploit the widely used Dynamic Partial Reconfiguration (DPR) support in Field Programmable Gate Arrays (FPGAs) to implant a hardware Trojan in an Advanced Encryption Standard (AES) encryptioncircuit implemented on a FPGA. The DPR is performed by transferring the required partial configuration bitstream file over an Ethernet connection to the FPGA board, from an attacker{\textquoteright}s computer which can communicate with the FPGAover a network. The inserted Trojan launches a “fault attack” on the AES encryption circuit, which enables recovery of the secret key by standard mathematical analysis of the faulty ciphertext produced. To the best of our knowledge, this is the first reported attack which exploits DPR to breakan AES hardware implementation on FPGA. Our implementation results establish this to be an extremely potent attack on AES at low hardware and computational overhead, while using the standard unlicensed FPGA design tools.",

keywords = "Hardware Trojan, FPGA, Dynamic Partial Reconfiguration, AES, Fault Attack",

author = "Johnson, {Anju P.} and Sayandeep Saha and Chakraborty, {Rajat Subhra} and Debdeep Mukhopadhyay and Sezer G{\"o}ren",

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T1 - Fault Attack on AES via Hardware Trojan Insertion by Dynamic Partial Reconfiguration of FPGA over Ethernet

AU - Johnson, Anju P.

AU - Saha, Sayandeep

AU - Chakraborty, Rajat Subhra

AU - Mukhopadhyay, Debdeep

AU - Gören, Sezer

PY - 2014/10

Y1 - 2014/10

N2 - We describe a novel methodology to exploit the widely used Dynamic Partial Reconfiguration (DPR) support in Field Programmable Gate Arrays (FPGAs) to implant a hardware Trojan in an Advanced Encryption Standard (AES) encryptioncircuit implemented on a FPGA. The DPR is performed by transferring the required partial configuration bitstream file over an Ethernet connection to the FPGA board, from an attacker’s computer which can communicate with the FPGAover a network. The inserted Trojan launches a “fault attack” on the AES encryption circuit, which enables recovery of the secret key by standard mathematical analysis of the faulty ciphertext produced. To the best of our knowledge, this is the first reported attack which exploits DPR to breakan AES hardware implementation on FPGA. Our implementation results establish this to be an extremely potent attack on AES at low hardware and computational overhead, while using the standard unlicensed FPGA design tools.

AB - We describe a novel methodology to exploit the widely used Dynamic Partial Reconfiguration (DPR) support in Field Programmable Gate Arrays (FPGAs) to implant a hardware Trojan in an Advanced Encryption Standard (AES) encryptioncircuit implemented on a FPGA. The DPR is performed by transferring the required partial configuration bitstream file over an Ethernet connection to the FPGA board, from an attacker’s computer which can communicate with the FPGAover a network. The inserted Trojan launches a “fault attack” on the AES encryption circuit, which enables recovery of the secret key by standard mathematical analysis of the faulty ciphertext produced. To the best of our knowledge, this is the first reported attack which exploits DPR to breakan AES hardware implementation on FPGA. Our implementation results establish this to be an extremely potent attack on AES at low hardware and computational overhead, while using the standard unlicensed FPGA design tools.

KW - Hardware Trojan

KW - FPGA

KW - Dynamic Partial Reconfiguration

KW - AES

KW - Fault Attack

M3 - Conference contribution

SN - 9781450329323

BT - Workshop on Embedded Systems Security (WESS, part of ACM ESWEEK) 2014, New Delhi, India

PB - ACM

ER -