Field-Programmable Gate Array - Research Database, The University of York

By the same authors

A Novel Multi-objective Optimisation Algorithm for Routability and Timing Driven Circuit Clustering on FPGAs
Wang, Y., Trefzer, M. A., Bale, S. J., Walker, J. A. & Tyrrell, A. M., 17 Dec 2018
Article in IET Computers and Digital Techniques
An Evolutionary Approach to Runtime Variability Mapping and Mitigation on a Multi-Reconfigurable Architecture
Bale, S. J., Burmester Campos, P., Trefzer, M. A., Walker, J. A. & Tyrrell, A. M., 15 May 2017, Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, p. 1570-1575 6 p.
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration
Trefzer, M. A., Walker, J. A., Bale, S. J. & Tyrrell, A., Jul 2015
Article in IET Computers and Digital Techniques
High-Sigma Performance Analysis using Multi-Objective Evolutionary Algorithms
Trefzer, M. A., Tyrrell, A., Bale, S. J. & Walker, J. A., Jun 2015.
Research output: Contribution to conference › Poster
Multiobjective Genetic Algorithm for Routability-Driven Circuit Clustering on FPGAs
Wang, Y., Bale, S. J., Walker, J. A., Trefzer, M. A. & Tyrrell, A., 13 Jan 2015, IEEE International Conference on Evolvable Systems, Proceedings. IEEE, p. 109-116
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Field-Programmable Gate Array: WO2013064839

Research output: Other contribution

Author(s)

Department/unit(s)

Electronic Engineering

Publication details

Date	Published - 10 May 2013
Type	Patent
Original language	English

Abstract

An FPGA has a number of CLBs, each CLB having a number of CABs. Each CAB comprises: a number of configurable transistors each comprising one or more usable transistors M and a number of switching transistors; and, configuration circuitry comprising a number of switching transistors. The ratio of switching transistors to usable transistors for each CAB is less than 26:1. A method of configuring such an FPGA comprises optimising each configurable transistor.

Research areas

FPGA, reconfigurable architectures, patent

Projects

PAnDA: Programmable Analogue & Digital Array
Project: Research project (funded) › Research

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The York Research Database

By the same authors

A Novel Multi-objective Optimisation Algorithm for Routability and Timing Driven Circuit Clustering on FPGAs

An Evolutionary Approach to Runtime Variability Mapping and Mitigation on a Multi-Reconfigurable Architecture

Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration

High-Sigma Performance Analysis using Multi-Objective Evolutionary Algorithms

Multiobjective Genetic Algorithm for Routability-Driven Circuit Clustering on FPGAs