Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration

TY - JOUR

T1 - Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration

AU - Trefzer, Martin Albrecht

AU - Walker, James Alfred

AU - Bale, Simon Jonathan

AU - Tyrrell, Andy

N1 - This content is made available by the publisher under a Creative Commons CC-BY Licence

PY - 2015/7

Y1 - 2015/7

N2 - In this study, the authors present a design optimisation case study of D-type flip-flop timing characteristics that are degraded as a result of intrinsic stochastic variability in a 25 nm technology process. What makes this work unique is that the design is mapped onto a multi-reconfigurable architecture, which is, like a field programmable gate array (FPGA), configurable at the gate level but can then be optimised using transistor level configuration options that are additionally built into the architecture. While a hardware VLSI prototype of this architecture is currently being fabricated, the results presented here are obtained from a virtual prototype implemented in SPICE using statistically enhanced 25 nm high performance metal gate MOSFET compact models from gold standard simulations for pre-fabrication verification. A D-type flip-flop is chosen as a benchmark in this study, and it is shown that timing characteristics that are degraded because of stochastic variability can be recovered and improved. This study highlights significant potential of the programmable analogue and digital array architecture to represent a next-generation FPGA architecture that can recover yield using post-fabrication transistor-level optimisation in addition to adjusting the operating point of mapped designs.

AB - In this study, the authors present a design optimisation case study of D-type flip-flop timing characteristics that are degraded as a result of intrinsic stochastic variability in a 25 nm technology process. What makes this work unique is that the design is mapped onto a multi-reconfigurable architecture, which is, like a field programmable gate array (FPGA), configurable at the gate level but can then be optimised using transistor level configuration options that are additionally built into the architecture. While a hardware VLSI prototype of this architecture is currently being fabricated, the results presented here are obtained from a virtual prototype implemented in SPICE using statistically enhanced 25 nm high performance metal gate MOSFET compact models from gold standard simulations for pre-fabrication verification. A D-type flip-flop is chosen as a benchmark in this study, and it is shown that timing characteristics that are degraded because of stochastic variability can be recovered and improved. This study highlights significant potential of the programmable analogue and digital array architecture to represent a next-generation FPGA architecture that can recover yield using post-fabrication transistor-level optimisation in addition to adjusting the operating point of mapped designs.

KW - flip-flops; MOSFET; field programmable gate arrays

KW - intrinsic stochastic variability; integrated circuit emphasis; hardware VLSI prototype; gold standard simulations; transistor level configuration options; next-generation FPGA architecture; post-fabrication transistor-level optimisation; simulation progr

U2 - 10.1049/iet-cdt.2014.0146

DO - 10.1049/iet-cdt.2014.0146

M3 - Article

VL - 9

SP - 190

EP - 196

JO - IET Computers and Digital Techniques

JF - IET Computers and Digital Techniques

SN - 1751-8601

IS - 4

ER -