Fine-Grained Link Locking Within Power and Latency Transaction Level Modelling in Wormhole Switching Non-Preemptive Networks On Chip

TY - GEN

T1 - Fine-Grained Link Locking Within Power and Latency Transaction Level Modelling in Wormhole Switching Non-Preemptive Networks On Chip

AU - Harbin, James Robert

AU - Soares Indrusiak, Leandro

PY - 2014

Y1 - 2014

N2 - An increasingly time-consuming part of the design flow of on-chip multiprocessors is simulation of the network on chip (NoC) architecture. Cycle-accurate simulation of state-of-the art network-on-chip interconnects can be prohibitively slow for realistic application examples. In this paper, we identify a time-predictable non-preemptive network-on-chip architecture and propose a TLM model with fine-grained locking of links. The model is tested via simulation of two benchmark application scenarios. Results demonstrate that the proposed algorithm can model the latency upon the majority of flows very closely to the cycle-accurate model, while providing more than 97% accurate power consumption modelling even on the worst case links. This is achieved while simulating nearly three orders of magnitude faster compared to a cycle-accurate model of the same interconnect.

AB - An increasingly time-consuming part of the design flow of on-chip multiprocessors is simulation of the network on chip (NoC) architecture. Cycle-accurate simulation of state-of-the art network-on-chip interconnects can be prohibitively slow for realistic application examples. In this paper, we identify a time-predictable non-preemptive network-on-chip architecture and propose a TLM model with fine-grained locking of links. The model is tested via simulation of two benchmark application scenarios. Results demonstrate that the proposed algorithm can model the latency upon the majority of flows very closely to the cycle-accurate model, while providing more than 97% accurate power consumption modelling even on the worst case links. This is achieved while simulating nearly three orders of magnitude faster compared to a cycle-accurate model of the same interconnect.

U2 - 10.1145/2556863.2556865

DO - 10.1145/2556863.2556865

M3 - Conference contribution

SN - 978-1-4503-2607-0

SP - 33

EP - 38

BT - PARMA-DITAM '14 Proceedings of Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms

PB - ACM

ER -