FPGA design of box‐constrained DCD‐based detector for large‐scale MIMO systems

Zhi Quan; Yuriy Zakharov

doi:10.1002/2016RS006021

FPGA design of box‐constrained DCD‐based detector for large‐scale MIMO systems

Zhi Quan, Yuriy Zakharov

Electronic Engineering

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Abstract

This paper proposes an improved architecture of a low‐complexity box‐constrained multiple‐input multiple‐output (MIMO) detector which is based on the dichotomous coordinate descent (DCD) algorithm. This architecture allows a simple field‐programmable gate‐array implementation of the detector and explores the parallel implementation to reduce the number of clock cycles required in the design. We investigate the proposed design and compare its detection performance, hardware resources, and convergence speed with that of known designs. It is shown that the proposed design provides improvement in the detection performance compared to the minimum mean square error (MMSE) detector. The numerical results also show that the proposed architecture requires as few as 184, 210, and 223 slices for 16 × 16, 64 × 64, and 128 × 128 MIMO systems, respectively, which is significantly less than that required by known designs of the MMSE detector. By comparing the serial and parallel implementations of the box‐constrained detector, we show that the parallel implementation requires 15% fewer clock cycles.

Original language	English
Pages (from-to)	918-926
Number of pages	9
Journal	Radio Science
Volume	51
Issue number	7
DOIs	https://doi.org/10.1002/2016RS006021
Publication status	Published - 1 Jul 2016

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10.1002/2016RS006021

Cite this

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title = "FPGA design of box‐constrained DCD‐based detector for large‐scale MIMO systems",

abstract = "This paper proposes an improved architecture of a low‐complexity box‐constrained multiple‐input multiple‐output (MIMO) detector which is based on the dichotomous coordinate descent (DCD) algorithm. This architecture allows a simple field‐programmable gate‐array implementation of the detector and explores the parallel implementation to reduce the number of clock cycles required in the design. We investigate the proposed design and compare its detection performance, hardware resources, and convergence speed with that of known designs. It is shown that the proposed design provides improvement in the detection performance compared to the minimum mean square error (MMSE) detector. The numerical results also show that the proposed architecture requires as few as 184, 210, and 223 slices for 16 × 16, 64 × 64, and 128 × 128 MIMO systems, respectively, which is significantly less than that required by known designs of the MMSE detector. By comparing the serial and parallel implementations of the box‐constrained detector, we show that the parallel implementation requires 15% fewer clock cycles. ",

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