Abstract
The development and validation of fault-tolerant computers for critical real-time applications are currently both costly and time consuming. Often, the underlying technology is out-of-date by the time the computers are ready for deployment. Obsolescence can become a chronic problem when the systems in which they are embedded have lifetimes of several decades. This paper gives an overview of the work carried-out in a project that is tackling the issues of cost and rapid obsolescence by defining a generic fault-tolerant computer architecture based essentially on commercial off-the-shelf (COTS) components (both processor hardware boards and real-time operating systems). The architecture uses a limited number of specific, but generic, hardware and software components to implement an architecture that can be configured along three dimensions: redundant channels, redundant lanes, and integrity levels. The two dimensions-of physical redundancy allow the definition of a wide variety of instances with different fault tolerance strategies. The integrity level dimension allows application components of different levels of criticality to coexist in the same instance. The paper describes the main concepts of the architecture, the supporting environments for development and validation, and the prototypes currently being implemented.
| Original language | English |
|---|---|
| Pages (from-to) | 580-599 |
| Number of pages | 20 |
| Journal | IEEE Transactions on Parallel and Distributed Systems |
| Volume | 10 |
| Issue number | 6 |
| Publication status | Published - Jun 1999 |
Keywords
- computer architecture
- generic architecture
- embedded systems
- fault tolerance
- real-time
- integrity levels
- FAULT INJECTION