By the same authors

Hardware implementation of the Ravenscar Ada tasking profile

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Author(s)

Department/unit(s)

Publication details

Title of host publicationProceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002
DatePublished - 2002
Pages59-68
Number of pages10
PublisherACM
EditorsShuvra S. Bhattacharyya, Trevor N. Mudge, Wayne Wolf, Ahmed Amine Jerraya
Original languageUndefined/Unknown

Abstract

Real-Time Systems place large demands on the languages used to implement them. Processor based implementation methods do not allow accurate timing analysis of systems due to the complexity of modern processors. FPGAs provide a means to implement a real-time system in a way that allows accurate timing analysis to be performed.Existing hardware implementations of high-level programming languages do not support the needs of real-time systems. This paper presents a hardware implementation of the SPARK Ravenscar subsets of Ada which can be accurately analysed for its timing properties. A method of compiling sequential Ada programs has been described elsewhere [21], and this is expanded to include the compilation of protected objects and tasks. The effect this has on the ability to analyse the timing of the program is then examined.

Discover related content

Find related publications, people, projects, datasets and more using interactive charts.

View graph of relations