Hardware-Accelerated Response Time Analysis for priority-preemptive Networks-on-Chip

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Published copy (DOI)



Publication details

Title of host publication10th International Symposium on Reconfigurable and Communication-centric Systems-on-Chip, ReCoSoC 2015
DatePublished - 2 Sep 2015
Number of pages8
PublisherInstitute of Electrical and Electronics Engineers Inc.
Original languageEnglish
ISBN (Print)9781467379427


End-To-End Response Time Analysis (E2ERTA) can be used to examine the timing performance of a Network-on-Chip (NoC). The complexity of its calculation increases with the scaling of both the task set and core count of the NoC. This paper presents a hardware implementation of E2ERTA along with two other acceleration schemes to reduce the computation time. We explore the performance of the proposed approach, and analyse its effectiveness against the state-of-The-Art in the field. The results show a significant improvement in analysing the timing performance, thus potentially enabling the use of E2ERTA as a fast and guaranteed deterministic admission controller for open and dynamic real-Time systems.

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