Hierarchical Strategies for Efficient Fault Recovery on the Reconfigurable PAnDA Device

TY - JOUR

T1 - Hierarchical Strategies for Efficient Fault Recovery on the Reconfigurable PAnDA Device

AU - Trefzer, Martin Albrecht

AU - Lawson, David Michael Renwick

AU - Bale, Simon Jonathan

AU - Walker, James

AU - Tyrrell, Andrew Martin

N1 - © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.

PY - 2017/6/1

Y1 - 2017/6/1

N2 - A novel hierarchical fault-tolerance methodology for reconfigurable devices is presented. A bespoke multi-reconfigurable FPGA architecture, the programmable analogue and digital array (PAnDA), is introduced allowing fine-grained reconfiguration beyond any other FPGA architecture currently in existence. Fault blind circuit repair strategies, which require no specific information of the nature or location of faults, are developed, exploiting architectural features of PAnDA. Two fault recovery techniques, stochastic and deterministic strategies, are proposed and results of each, as well as a comparison of the two, are presented. Both approaches are based on creating algorithms performing fine-grained hierarchical partial reconfiguration on faulty circuits in order to repair them. While the stochastic approach provides insights into feasibility of the method, the deterministic approach aims to generate optimal repair strategies for generic faults induced into a specific circuit. It is shown that both techniques successfully repair the benchmark circuits used after random faults are induced in random circuit locations, and the deterministic strategies are shown to operate efficiently and effectively after optimisation for a specific use case. The methods are shown to be generally applicable to any circuit on PAnDA, and to be straightforwardly customisable for any FPGA fabric providing some regularity and symmetry in its structure.

AB - A novel hierarchical fault-tolerance methodology for reconfigurable devices is presented. A bespoke multi-reconfigurable FPGA architecture, the programmable analogue and digital array (PAnDA), is introduced allowing fine-grained reconfiguration beyond any other FPGA architecture currently in existence. Fault blind circuit repair strategies, which require no specific information of the nature or location of faults, are developed, exploiting architectural features of PAnDA. Two fault recovery techniques, stochastic and deterministic strategies, are proposed and results of each, as well as a comparison of the two, are presented. Both approaches are based on creating algorithms performing fine-grained hierarchical partial reconfiguration on faulty circuits in order to repair them. While the stochastic approach provides insights into feasibility of the method, the deterministic approach aims to generate optimal repair strategies for generic faults induced into a specific circuit. It is shown that both techniques successfully repair the benchmark circuits used after random faults are induced in random circuit locations, and the deterministic strategies are shown to operate efficiently and effectively after optimisation for a specific use case. The methods are shown to be generally applicable to any circuit on PAnDA, and to be straightforwardly customisable for any FPGA fabric providing some regularity and symmetry in its structure.

KW - Circuit faults

KW - Computer architecture

KW - Routing

KW - Field programmable gate arrays

KW - Maintenance engineering

KW - Transistors

KW - Fabrics

KW - FPGA

KW - Special-Purpose and Application-Based Systems

KW - Performance of Systems

KW - Reconfigurable Computing Architectures

KW - Reconfigurable Hardware

KW - Fault tolerance

UR - http://www.scopus.com/inward/record.url?scp=85028041816&partnerID=8YFLogxK

U2 - 10.1109/TC.2016.2632722

DO - 10.1109/TC.2016.2632722

M3 - Article

SN - 0018-9340

VL - 66

SP - 930

EP - 945

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

IS - 6

M1 - 7756359

ER -