Homeostatic Fault Tolerance in Spiking Neural Networks: A Dynamic Hardware Perspective

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Fault tolerance is a remarkable feature of biological systems and their self-repair capability influence modern electronic systems. In this paper, we propose a novel plastic neural network model, which establishes homeostasis in a spiking neural network. Combined with this plasticity and the inspiration from inhibitory interneurons, we develop a fault-resilient robotic controller implemented on an FPGA establishing obstacle avoidance task. We demonstrate the proposed methodology on a spiking neural network implemented on Xilinx Artix-7 FPGA. The system is able to maintain stable firing (tolerance ±10%) with a loss of up to 75% of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware overhead with a tuning circuit (repair unit) which consumes only three slices/neuron for implementing a threshold voltage-based homeostatic fault-tolerant unit. The overall architecture has a minimal impact on power consumption and, therefore, supports scalable implementations. This paper opens a novel way of implementing the behavior of natural fault tolerant system in hardware establishing homeostatic self-repair behavior.

Original languageEnglish
Article number7995041
Pages (from-to)687-699
Number of pages13
JournalIeee transactions on circuits and systems i-Regular papers
Issue number2
Early online date28 Jul 2017
Publication statusPublished - 1 Feb 2018


  • FPGA
  • Self-repair
  • bio-inspired engineering
  • dynamic partial reconfiguration
  • fault tolerance
  • homeostasis
  • mixed-mode clock manager
  • phase locked loop

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