Homeostatic Fault Tolerance in Spiking Neural Networks: A Dynamic Hardware Perspective

TY - JOUR

T1 - Homeostatic Fault Tolerance in Spiking Neural Networks

T2 - A Dynamic Hardware Perspective

AU - Johnson, Anju Pulikkakudi

AU - Liu, Junxiu

AU - Millard, Alan Gregory

AU - Karim, Shvan

AU - Tyrrell, Andrew Martin

AU - Harkin, Jim

AU - Timmis, Jonathan Ian

AU - McDaid, Liam

AU - Halliday, David Malcolm

PY - 2018/2/1

Y1 - 2018/2/1

N2 - Fault tolerance is a remarkable feature of biological systems and their self-repair capability influence modern electronic systems. In this paper, we propose a novel plastic neural network model, which establishes homeostasis in a spiking neural network. Combined with this plasticity and the inspiration from inhibitory interneurons, we develop a fault-resilient robotic controller implemented on an FPGA establishing obstacle avoidance task. We demonstrate the proposed methodology on a spiking neural network implemented on Xilinx Artix-7 FPGA. The system is able to maintain stable firing (tolerance ±10%) with a loss of up to 75% of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware overhead with a tuning circuit (repair unit) which consumes only three slices/neuron for implementing a threshold voltage-based homeostatic fault-tolerant unit. The overall architecture has a minimal impact on power consumption and, therefore, supports scalable implementations. This paper opens a novel way of implementing the behavior of natural fault tolerant system in hardware establishing homeostatic self-repair behavior.

AB - Fault tolerance is a remarkable feature of biological systems and their self-repair capability influence modern electronic systems. In this paper, we propose a novel plastic neural network model, which establishes homeostasis in a spiking neural network. Combined with this plasticity and the inspiration from inhibitory interneurons, we develop a fault-resilient robotic controller implemented on an FPGA establishing obstacle avoidance task. We demonstrate the proposed methodology on a spiking neural network implemented on Xilinx Artix-7 FPGA. The system is able to maintain stable firing (tolerance ±10%) with a loss of up to 75% of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware overhead with a tuning circuit (repair unit) which consumes only three slices/neuron for implementing a threshold voltage-based homeostatic fault-tolerant unit. The overall architecture has a minimal impact on power consumption and, therefore, supports scalable implementations. This paper opens a novel way of implementing the behavior of natural fault tolerant system in hardware establishing homeostatic self-repair behavior.

KW - FPGA

KW - Self-repair

KW - bio-inspired engineering

KW - dynamic partial reconfiguration

KW - fault tolerance

KW - homeostasis

KW - mixed-mode clock manager

KW - phase locked loop

UR - http://ieeexplore.ieee.org/document/7995041/

UR - http://www.scopus.com/inward/record.url?scp=85028947387&partnerID=8YFLogxK

U2 - 10.1109/TCSI.2017.2726763

DO - 10.1109/TCSI.2017.2726763

M3 - Article

SN - 1549-8328

VL - 65

SP - 687

EP - 699

JO - Ieee transactions on circuits and systems i-Regular papers

JF - Ieee transactions on circuits and systems i-Regular papers

IS - 2

M1 - 7995041

ER -