Implementation of Reduced Precision Integer Epigenetic Networks in Hardware

TY - GEN

T1 - Implementation of Reduced Precision Integer Epigenetic Networks in Hardware

AU - Walter, Andrew

AU - Bale, Simon Jonathan

AU - Tyrrell, Andy

PY - 2021/12/6

Y1 - 2021/12/6

N2 - This paper details the development of a resource efficient implementation of the Artificial Epigenetic Network (AEN) concept, based on reduced precision integer mathematics, and the translation of this implementation into hardware via a Field Programmable Gate Array (FPGA) to provide improvements in resource utilisation and execution speed while not sacrificing the unique benefits provided by the epigenetic mechanism. Validation of the implementation’s performance on the inverted pendulum task is obtained and compared to that of previous AENs, as well as experiments to determine how far the precision of the network may be reduced while still maintaining an acceptable degree of performance.

AB - This paper details the development of a resource efficient implementation of the Artificial Epigenetic Network (AEN) concept, based on reduced precision integer mathematics, and the translation of this implementation into hardware via a Field Programmable Gate Array (FPGA) to provide improvements in resource utilisation and execution speed while not sacrificing the unique benefits provided by the epigenetic mechanism. Validation of the implementation’s performance on the inverted pendulum task is obtained and compared to that of previous AENs, as well as experiments to determine how far the precision of the network may be reduced while still maintaining an acceptable degree of performance.

KW - Artificial Epigenetic Networks

KW - Field Programable Gate Array

KW - Reduced Precision Computation

KW - Digital Hardware

M3 - Conference contribution

BT - IEEE International Conference on Evolvable Systems

PB - IEEE

CY - Orlando

ER -