Embryonic arrays display the desirable biological characteristics of fault-tolerance and a complex structure. They do not generally make use of a further biological characteristic; fundamentally asynchronous operation. Further to the inherent advantages of an asynchronous approach, scalability and reliability are perceived as benefits pertinent to embryonic designs.
This paper advances a simulated asynchronous embryonic design by realising its functional logic using a Xilinx Virtex FPGA. The AARDVArc program augments the standard design tools to achieve this macromodule based implementation. The design is compared to a similar synchronous design in terms of its logic requirement and performance. Although requiring additional resources and operating less quickly than its synchronous counterpart, this work forms the basis for a fully asynchronous practical embryonic array.
|Title of host publication
|2002 NASA/DOD CONFERENCE ON EVOLABLE HARDWARE, PROCEEDINGS
|A Stoica, J Lohn, R Katz, D Keymeulen, RS Zebulum
|Place of Publication
|IEEE Computer Society
|Number of pages
|Published - 2002
|NASA/DOD Conference on Evolvable Hardware - ALEXANDRIA
Duration: 15 Jul 2002 → 18 Jul 2002
|NASA/DOD Conference on Evolvable Hardware
|15/07/02 → 18/07/02