Implementing asynchronous embryonic circuits using AARDVArc

A H Jackson; A M Tyrrell

Implementing asynchronous embryonic circuits using AARDVArc

Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Embryonic arrays display the desirable biological characteristics of fault-tolerance and a complex structure. They do not generally make use of a further biological characteristic; fundamentally asynchronous operation. Further to the inherent advantages of an asynchronous approach, scalability and reliability are perceived as benefits pertinent to embryonic designs.

This paper advances a simulated asynchronous embryonic design by realising its functional logic using a Xilinx Virtex FPGA. The AARDVArc program augments the standard design tools to achieve this macromodule based implementation. The design is compared to a similar synchronous design in terms of its logic requirement and performance. Although requiring additional resources and operating less quickly than its synchronous counterpart, this work forms the basis for a fully asynchronous practical embryonic array.

Original language	English
Title of host publication	2002 NASA/DOD CONFERENCE ON EVOLABLE HARDWARE, PROCEEDINGS
Editors	A Stoica, J Lohn, R Katz, D Keymeulen, RS Zebulum
Place of Publication	LOS ALAMITOS
Publisher	IEEE Computer Society
Pages	231-240
Number of pages	10
ISBN (Print)	0-7695-1718-8
Publication status	Published - 2002
Event	NASA/DOD Conference on Evolvable Hardware - ALEXANDRIA Duration: 15 Jul 2002 → 18 Jul 2002

Conference

Conference	NASA/DOD Conference on Evolvable Hardware
City	ALEXANDRIA
Period	15/07/02 → 18/07/02

Cite this

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title = "Implementing asynchronous embryonic circuits using AARDVArc",

abstract = "Embryonic arrays display the desirable biological characteristics of fault-tolerance and a complex structure. They do not generally make use of a further biological characteristic; fundamentally asynchronous operation. Further to the inherent advantages of an asynchronous approach, scalability and reliability are perceived as benefits pertinent to embryonic designs.This paper advances a simulated asynchronous embryonic design by realising its functional logic using a Xilinx Virtex FPGA. The AARDVArc program augments the standard design tools to achieve this macromodule based implementation. The design is compared to a similar synchronous design in terms of its logic requirement and performance. Although requiring additional resources and operating less quickly than its synchronous counterpart, this work forms the basis for a fully asynchronous practical embryonic array.",

author = "Jackson, {A H} and Tyrrell, {A M}",

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booktitle = "2002 NASA/DOD CONFERENCE ON EVOLABLE HARDWARE, PROCEEDINGS",

publisher = "IEEE Computer Society",

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note = "NASA/DOD Conference on Evolvable Hardware ; Conference date: 15-07-2002 Through 18-07-2002",

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TY - GEN

T1 - Implementing asynchronous embryonic circuits using AARDVArc

AU - Jackson, A H

AU - Tyrrell, A M

PY - 2002

Y1 - 2002

N2 - Embryonic arrays display the desirable biological characteristics of fault-tolerance and a complex structure. They do not generally make use of a further biological characteristic; fundamentally asynchronous operation. Further to the inherent advantages of an asynchronous approach, scalability and reliability are perceived as benefits pertinent to embryonic designs.This paper advances a simulated asynchronous embryonic design by realising its functional logic using a Xilinx Virtex FPGA. The AARDVArc program augments the standard design tools to achieve this macromodule based implementation. The design is compared to a similar synchronous design in terms of its logic requirement and performance. Although requiring additional resources and operating less quickly than its synchronous counterpart, this work forms the basis for a fully asynchronous practical embryonic array.

AB - Embryonic arrays display the desirable biological characteristics of fault-tolerance and a complex structure. They do not generally make use of a further biological characteristic; fundamentally asynchronous operation. Further to the inherent advantages of an asynchronous approach, scalability and reliability are perceived as benefits pertinent to embryonic designs.This paper advances a simulated asynchronous embryonic design by realising its functional logic using a Xilinx Virtex FPGA. The AARDVArc program augments the standard design tools to achieve this macromodule based implementation. The design is compared to a similar synchronous design in terms of its logic requirement and performance. Although requiring additional resources and operating less quickly than its synchronous counterpart, this work forms the basis for a fully asynchronous practical embryonic array.

M3 - Conference contribution

SN - 0-7695-1718-8

SP - 231

EP - 240

BT - 2002 NASA/DOD CONFERENCE ON EVOLABLE HARDWARE, PROCEEDINGS

A2 - Stoica, A

A2 - Lohn, J

A2 - Katz, R

A2 - Keymeulen, D

A2 - Zebulum, RS

PB - IEEE Computer Society

CY - LOS ALAMITOS

T2 - NASA/DOD Conference on Evolvable Hardware

Y2 - 15 July 2002 through 18 July 2002

ER -