Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers

TY - GEN

T1 - Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers

AU - Moller, Leandro

AU - Fischer, Peter

AU - Moraes, Fernando

AU - Indrusiak, Leandro Soares

AU - Glesner, Manfred

PY - 2010

Y1 - 2010

N2 - Networks-on-Chip (NoC) allow several data transfers to occur in parallel and are indeed the communication infra-structure of future hundred-cores Systems-on-Chip (SoCs). However, if specialized modules are sending data at full speed to the NoC, Quality of Service (QoS) can be no longer guaranteed. This work presents a multi-layer mesh NoC approach to improve the QoS of such communication hungry SoCs. While one mesh layer is fixed in the system for control purposes, other data layers can be configured at runtime to provide the desired data throughput required by the application. This is accomplished by partially and dynamically reconfiguring the data layer routers. Arbitration algorithms, routing algorithms and huge crossbars are removed from the data layer routers, because all data routers in the path a configured accordingly before its utilization. A SoC following this idea was prototyped in a Virtex-4 FPGA and the Early Access Partial Flow was used to partially and dynamically reconfigure the NoC. We show that 120 (5!) different configurations are needed for each reconfigurable router with 5 bidirectional ports. Each configuration requires 33KB of memory and occupies 32 CLBs of area.

AB - Networks-on-Chip (NoC) allow several data transfers to occur in parallel and are indeed the communication infra-structure of future hundred-cores Systems-on-Chip (SoCs). However, if specialized modules are sending data at full speed to the NoC, Quality of Service (QoS) can be no longer guaranteed. This work presents a multi-layer mesh NoC approach to improve the QoS of such communication hungry SoCs. While one mesh layer is fixed in the system for control purposes, other data layers can be configured at runtime to provide the desired data throughput required by the application. This is accomplished by partially and dynamically reconfiguring the data layer routers. Arbitration algorithms, routing algorithms and huge crossbars are removed from the data layer routers, because all data routers in the path a configured accordingly before its utilization. A SoC following this idea was prototyped in a Virtex-4 FPGA and the Early Access Partial Flow was used to partially and dynamically reconfigure the NoC. We show that 120 (5!) different configurations are needed for each reconfigurable router with 5 bidirectional ports. Each configuration requires 33KB of memory and occupies 32 CLBs of area.

UR - http://www.scopus.com/inward/record.url?scp=79951765342&partnerID=8YFLogxK

U2 - 10.1109/FPL.2010.53

DO - 10.1109/FPL.2010.53

M3 - Conference contribution

SN - 978-1-4244-7842-2

SP - 229

EP - 233

BT - 2010 International Conference on Field Programmable Logic and Applications (FPL)

T2 - 2010 International Conference on Field Programmable Logic and Applications (FPL)

Y2 - 31 August 2010 through 2 September 2010

ER -