Improving the Performance of Embedded Superscalatr Microprocessors by Adding Partial Pipeline

Christopher Crispin-Bailey, Huibin Shi, Neil Hastie, Glenn Farrel

Research output: Contribution to conferencePaperpeer-review

Abstract

This paper introduces adding a “partial” pipeline to a
base embedded superscalar microprocessor
implementation to achieve cost effective performance
improvements. This method is exemplified by adding a
“partial” integer pipeline (IP) to the TriCore TM 2.0
MCU/DSP core. The “partial” IP pipeline, designed
based on TriCore 2.0 simulation results of the EEMBC
benchmark suite, executes a subset of TriCore 2.0 IP
instructions. We used the basic block sampling and
simulation technique to simulate enhanced TriCore 2.0
models, and obtained results indicating that adding the
partial IP pipeline can achieve similar performance
improvements to duplicating the full IP pipeline. Our
approach can be applied to the early design stages of
microprocessor development in order to explore design
spaces.
Original languageEnglish
Pages15-20
Number of pages6
Publication statusPublished - 31 Aug 2005
EventFirst ERCIM Workshop on Software-Intensive Dependable Embedded Systems - Porto, Portugal
Duration: 30 Aug 20053 Sept 2005

Conference

ConferenceFirst ERCIM Workshop on Software-Intensive Dependable Embedded Systems
Country/TerritoryPortugal
CityPorto
Period30/08/053/09/05

Cite this