Abstract
This work investigates the reduction of power consumption in Networks-on-Chip through the reduction of transition activity using data coding schemes. Power macromodels for NoC and encoding modules were built, allowing the estimation of the power consumption as a function of the transition activity at each module input. Power macromodels are embedded in a system model and a set of simulations are performed, analyzing the trade-off between the power savings due to coding schemes versus the power consumption overhead due to the encoding and decoding modules.
Original language | English |
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Title of host publication | IEEE Computer Society Annual Symposium on VLSI, Proceedings |
Place of Publication | LOS ALAMITOS |
Publisher | IEEE Computer Society |
Pages | 299-304 |
Number of pages | 6 |
ISBN (Print) | 978-0-7695-2896-0 |
Publication status | Published - 2007 |
Keywords
- ON-CHIP