Instruction level parallelism of stack-code under varied issue widths, and one-level branch prediction

Chris Bailey, Huibin Shi

Research output: Contribution to conferencePaperpeer-review


Stack architecture research interests have surfaced again in recent years, however stack machines are generally regarded as sequential execution architectures. By assuming that ILP (Instruction-Level Parallelism) can be exploited in a stack machine, we are able to use static analysis to uncover and measure available such instruction level parallelism as it naturally exists in the stack code of a hypothetical architecture. With increasing issue widths, a superscalar stack machine is shown to be modestly scalable, and displays improved scalability with the impact of branch prediction considered. This paper also indicates some of the limitations of the issue width expansion, which is confined by the available ILP of the stack code.
Original languageUndefined/Unknown
Publication statusPublished - 2005

Bibliographical note

ISBN: 972-99353-6-X

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