Abstract
State-of-the-art electronic design allows the integration
of complex electronic systems comprising thousands of highlevel
functions on a single chip. Key enabling factors making
this possible are advanced CMOS VLSI technology nodes and
electronic design automation (EDA) tools that can handle the
level of complexity by breaking down a system into blocks, subblocks
or cells. However, due to abstraction this can prevent
a design from making full use of the capabilities of the process
technology. In this work we propose a method to address this. An
automated design approach is presented using a multi-objective
(MO) evolutionary algorithm at the digital layout level for a
simple CMOS VLSI design. NSGA-II is applied to optimise the
circuit by performing structural adjustments on a parametrised
layout to create circuit instances representing optimal trade-offs
between speed, power consumption and area. Optimising at the
physical layout level ensures that the circuits generated can be
both manufactured and that measured performance is realistic.
The specific focus of this paper is to provide a feasibility study
of the parametric layout approach in the context of MO, and
results for a 1-bit full adder cell are shown. We anticipate this to
be the first step to produce optimised libraries of cells that can
be used to improve circuit performance at higher design levels
in the future.
of complex electronic systems comprising thousands of highlevel
functions on a single chip. Key enabling factors making
this possible are advanced CMOS VLSI technology nodes and
electronic design automation (EDA) tools that can handle the
level of complexity by breaking down a system into blocks, subblocks
or cells. However, due to abstraction this can prevent
a design from making full use of the capabilities of the process
technology. In this work we propose a method to address this. An
automated design approach is presented using a multi-objective
(MO) evolutionary algorithm at the digital layout level for a
simple CMOS VLSI design. NSGA-II is applied to optimise the
circuit by performing structural adjustments on a parametrised
layout to create circuit instances representing optimal trade-offs
between speed, power consumption and area. Optimising at the
physical layout level ensures that the circuits generated can be
both manufactured and that measured performance is realistic.
The specific focus of this paper is to provide a feasibility study
of the parametric layout approach in the context of MO, and
results for a 1-bit full adder cell are shown. We anticipate this to
be the first step to produce optimised libraries of cells that can
be used to improve circuit performance at higher design levels
in the future.
| Original language | English |
|---|---|
| Pages | 1339-1345 |
| Number of pages | 7 |
| Publication status | Published - Nov 2018 |
| Event | 2018 SYMPOSIUM SERIES ON COMPUTATIONAL INTELLIGENCE - Sheraton Grand Bangalore Hotel @ Brigade Gateway, Bengaluru, India Duration: 18 Nov 2018 → 21 Nov 2018 http://ieee-ssci2018.org/ |
Conference
| Conference | 2018 SYMPOSIUM SERIES ON COMPUTATIONAL INTELLIGENCE |
|---|---|
| Abbreviated title | IEEE-SSCI 2018 |
| Country/Territory | India |
| City | Bengaluru |
| Period | 18/11/18 → 21/11/18 |
| Internet address |
Keywords
- VLSI
- Multi-objective optimization
- Evolutionary algorithm
- GENETIC ALGORITHM
- microbial GA
- Physical layout