Investigating available instruction level parallelism for stack based machine architectures

H Shi; C Bailey

Investigating available instruction level parallelism for stack based machine architectures

Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Stack architectures have attracted much renewed research in recent years, due largely to the arrival of the JAVA programming language for Internet, and more recently in embedded applications. However, instruction level parallelism (ILP) has not yet received significant attention with respect to such machines. We have developed a stack code viewer/analyzer tool to analyze available ILP in stack assembler-code, together with the UTSA simulator, under unlimited software and hardware resource configurations. Results for basic block analysis reveal marginal speedups of available ILP over the serial execution in the absence of mechanisms for branch speculation or code optimization. Results for superblock and loop unrolling techniques show that more significant improvements can be made to available parallelism where effort is directed. An experiment is also presented to highlight the significance of branch prediction. In all tests, our stack code viewer/analyzer tool can graphically represent the scheduling result of each basic block.

Original language	English
Title of host publication	PROCEEDINGS OF THE EUROMICRO SYSTEMS ON DIGITAL SYSTEM DESIGN
Editors	H Selvaraj
Place of Publication	LOS ALAMITOS
Publisher	IEEE Computer Society
Pages	112-120
Number of pages	9
ISBN (Print)	0-7695-2203-3
Publication status	Published - 2004
Event	DSD 2004 - Rennes, France Duration: 31 Aug 2004 → 3 Sept 2004

Conference

Conference	DSD 2004
Country/Territory	France
City	Rennes
Period	31/08/04 → 3/09/04

Cite this

@inproceedings{0b8a327f5dae479dbefdf7bf1795e6f0,

title = "Investigating available instruction level parallelism for stack based machine architectures",

abstract = "Stack architectures have attracted much renewed research in recent years, due largely to the arrival of the JAVA programming language for Internet, and more recently in embedded applications. However, instruction level parallelism (ILP) has not yet received significant attention with respect to such machines. We have developed a stack code viewer/analyzer tool to analyze available ILP in stack assembler-code, together with the UTSA simulator, under unlimited software and hardware resource configurations. Results for basic block analysis reveal marginal speedups of available ILP over the serial execution in the absence of mechanisms for branch speculation or code optimization. Results for superblock and loop unrolling techniques show that more significant improvements can be made to available parallelism where effort is directed. An experiment is also presented to highlight the significance of branch prediction. In all tests, our stack code viewer/analyzer tool can graphically represent the scheduling result of each basic block.",

author = "H Shi and C Bailey",

year = "2004",

language = "English",

isbn = "0-7695-2203-3",

pages = "112--120",

editor = "H Selvaraj",

booktitle = "PROCEEDINGS OF THE EUROMICRO SYSTEMS ON DIGITAL SYSTEM DESIGN",

publisher = "IEEE Computer Society",

address = "United States",

note = "DSD 2004 ; Conference date: 31-08-2004 Through 03-09-2004",

}

TY - GEN

T1 - Investigating available instruction level parallelism for stack based machine architectures

AU - Shi, H

AU - Bailey, C

PY - 2004

Y1 - 2004

N2 - Stack architectures have attracted much renewed research in recent years, due largely to the arrival of the JAVA programming language for Internet, and more recently in embedded applications. However, instruction level parallelism (ILP) has not yet received significant attention with respect to such machines. We have developed a stack code viewer/analyzer tool to analyze available ILP in stack assembler-code, together with the UTSA simulator, under unlimited software and hardware resource configurations. Results for basic block analysis reveal marginal speedups of available ILP over the serial execution in the absence of mechanisms for branch speculation or code optimization. Results for superblock and loop unrolling techniques show that more significant improvements can be made to available parallelism where effort is directed. An experiment is also presented to highlight the significance of branch prediction. In all tests, our stack code viewer/analyzer tool can graphically represent the scheduling result of each basic block.

AB - Stack architectures have attracted much renewed research in recent years, due largely to the arrival of the JAVA programming language for Internet, and more recently in embedded applications. However, instruction level parallelism (ILP) has not yet received significant attention with respect to such machines. We have developed a stack code viewer/analyzer tool to analyze available ILP in stack assembler-code, together with the UTSA simulator, under unlimited software and hardware resource configurations. Results for basic block analysis reveal marginal speedups of available ILP over the serial execution in the absence of mechanisms for branch speculation or code optimization. Results for superblock and loop unrolling techniques show that more significant improvements can be made to available parallelism where effort is directed. An experiment is also presented to highlight the significance of branch prediction. In all tests, our stack code viewer/analyzer tool can graphically represent the scheduling result of each basic block.

M3 - Conference contribution

SN - 0-7695-2203-3

SP - 112

EP - 120

BT - PROCEEDINGS OF THE EUROMICRO SYSTEMS ON DIGITAL SYSTEM DESIGN

A2 - Selvaraj, H

PB - IEEE Computer Society

CY - LOS ALAMITOS

T2 - DSD 2004

Y2 - 31 August 2004 through 3 September 2004

ER -