Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms

Sanna Määttä; Leandro Moeller; Leandro Soares Indrusiak; Luciano Ost; Manfred Glesner; Jari Nurmi; Fernando Moraes

doi:10.4018/jertcs.2010103005

Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms

Sanna Määttä, Leandro Moeller, Leandro Soares Indrusiak, Luciano Ost, Manfred Glesner, Jari Nurmi, Fernando Moraes

Computer Science

Research output: Contribution to journal › Article › peer-review

Abstract

Application models are often disregarded during the design of multiprocessor Systems-on-Chip (MPSoC). This is due to the difficulties of capturing the application constraints and applying them to the design space exploration of the platform. In this article we propose an application modelling formalism that supports joint validation of application and platform models. To support designers on the trade-off analysis between accuracy, observability, and validation speed, we show that this approach can handle the successive refinement of platform models at multiple abstraction levels. A case study of the joint validation of a single application successively mapped onto three different platform models demonstrates the applicability of the presented approach.

Original language	English
Pages (from-to)	86-101
Number of pages	16
Journal	International Journal of Embedded and Real-Time Communication Systems (IJERTCS)
Volume	1
Issue number	1
DOIs	https://doi.org/10.4018/jertcs.2010103005
Publication status	Published - Jan 2010

Access to Document

10.4018/jertcs.2010103005

Cite this

@article{70b3651feb4e4e6190a5bc8dd7026e1c,

title = "Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms",

abstract = "Application models are often disregarded during the design of multiprocessor Systems-on-Chip (MPSoC). This is due to the difficulties of capturing the application constraints and applying them to the design space exploration of the platform. In this article we propose an application modelling formalism that supports joint validation of application and platform models. To support designers on the trade-off analysis between accuracy, observability, and validation speed, we show that this approach can handle the successive refinement of platform models at multiple abstraction levels. A case study of the joint validation of a single application successively mapped onto three different platform models demonstrates the applicability of the presented approach. ",

author = "Sanna M{\"a}{\"a}tt{\"a} and Leandro Moeller and {Soares Indrusiak}, Leandro and Luciano Ost and Manfred Glesner and Jari Nurmi and Fernando Moraes",

year = "2010",

month = jan,

doi = "10.4018/jertcs.2010103005",

language = "English",

volume = "1",

pages = "86--101",

journal = "International Journal of Embedded and Real-Time Communication Systems (IJERTCS)",

issn = "1947-3176",

publisher = "IGI Global Publishing",

number = "1",

}

TY - JOUR

T1 - Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms

AU - Määttä, Sanna

AU - Moeller, Leandro

AU - Soares Indrusiak, Leandro

AU - Ost, Luciano

AU - Glesner, Manfred

AU - Nurmi, Jari

AU - Moraes, Fernando

PY - 2010/1

Y1 - 2010/1

N2 - Application models are often disregarded during the design of multiprocessor Systems-on-Chip (MPSoC). This is due to the difficulties of capturing the application constraints and applying them to the design space exploration of the platform. In this article we propose an application modelling formalism that supports joint validation of application and platform models. To support designers on the trade-off analysis between accuracy, observability, and validation speed, we show that this approach can handle the successive refinement of platform models at multiple abstraction levels. A case study of the joint validation of a single application successively mapped onto three different platform models demonstrates the applicability of the presented approach.

AB - Application models are often disregarded during the design of multiprocessor Systems-on-Chip (MPSoC). This is due to the difficulties of capturing the application constraints and applying them to the design space exploration of the platform. In this article we propose an application modelling formalism that supports joint validation of application and platform models. To support designers on the trade-off analysis between accuracy, observability, and validation speed, we show that this approach can handle the successive refinement of platform models at multiple abstraction levels. A case study of the joint validation of a single application successively mapped onto three different platform models demonstrates the applicability of the presented approach.

UR - http://www.scopus.com/inward/record.url?scp=78650220877&partnerID=8YFLogxK

U2 - 10.4018/jertcs.2010103005

DO - 10.4018/jertcs.2010103005

M3 - Article

SN - 1947-3176

VL - 1

SP - 86

EP - 101

JO - International Journal of Embedded and Real-Time Communication Systems (IJERTCS)

JF - International Journal of Embedded and Real-Time Communication Systems (IJERTCS)

IS - 1

ER -

Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms

Abstract

Access to Document

Other files and links

Cite this