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This paper presents a comparison between conventional and multi-objective Cartesian Genetic Programming evolved designs for a 2-bit adder and a 2-bit multiplier. Each design is converted from a gate-level schematic to a transistor level implementation, through the use of an open-source standard cell library, and simulated in NGSPICE in order to generate industry standard metrics, such as propagation delay and dynamic power. Additionally, a statistical intrinsic variability analysis is performed, in order to see how each design is affected by intrinsic variability when fabricated at a cutting-edge technology node. The results show that the evolved design for the 2-bit adder is slower and consumes more power than the conventional design. The evolved design for the 2-bit multiplier was found to be faster but consumed more power than the conventional design, and that it was also more tolerant to the effects of intrinsic variability in both timing and power. This provides evidence that in the future, evolutionary-based approaches could be a feasible alternative for optimising designs at cutting-edge technology nodes, where traditional design methodologies are no longer appropriate, providing speed and power information about the standard cell library is used.
|Number of pages||12|
|Journal||9th International Conference on Evolvable Systems|
|Publication status||Published - Sep 2010|
- 1 Finished
NanoCMOS: Meeting the Design Challenges of ....
Tyrrell, A., Walker, J. A. & Hilder, J. A.
1/10/06 → 30/09/10
Project: Research project (funded) › Research