Memory-aware embedded control systems design

Research output: Contribution to journalArticle

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Memory-aware embedded control systems design. / Chang, Wanli; Goswami, Dip; Chakraborty, Samarjit; Ju, Lei; Xue, Jason; Andalam, Sidharta.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, No. 4, 27.09.2016, p. 586-599.

Research output: Contribution to journalArticle

Harvard

Chang, W, Goswami, D, Chakraborty, S, Ju, L, Xue, J & Andalam, S 2016, 'Memory-aware embedded control systems design', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 4, pp. 586-599. https://doi.org/10.1109/TCAD.2016.2613933

APA

Chang, W., Goswami, D., Chakraborty, S., Ju, L., Xue, J., & Andalam, S. (2016). Memory-aware embedded control systems design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36(4), 586-599. https://doi.org/10.1109/TCAD.2016.2613933

Vancouver

Chang W, Goswami D, Chakraborty S, Ju L, Xue J, Andalam S. Memory-aware embedded control systems design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2016 Sep 27;36(4):586-599. https://doi.org/10.1109/TCAD.2016.2613933

Author

Chang, Wanli ; Goswami, Dip ; Chakraborty, Samarjit ; Ju, Lei ; Xue, Jason ; Andalam, Sidharta. / Memory-aware embedded control systems design. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2016 ; Vol. 36, No. 4. pp. 586-599.

Bibtex - Download

@article{a85afe9288b2497cbf99567fe2db6238,
title = "Memory-aware embedded control systems design",
abstract = "Control applications are often implemented on highly cost-sensitive and resource-constrained embedded platforms, such as microcontrollers with a small on-chip memory. Typically, control algorithms are designed using model-based approaches, where the details of the implementation platform are completely ignored. As a result, optimizations that integrate platform-level characteristics into the control algorithms design are largely missing. With the emergence of cyber-physical systems (CPS)-oriented thinking, there has lately been a strong interest in co-design of control algorithms and their implementation platforms, leading to work on networked control systems and computation-aware control algorithms design. However, there has so far been no work on integrating the characteristics of a memory architecture into the design of control algorithms. In this paper we, for the first time, show that accounting for the impact of on-chip memory (or cache) reuse on the performance of control applications motivates new techniques for control algorithms design. This leads to significant improvement in quality of control for given resource availability, or more efficient implementations of embedded control applications. We believe that this paper opens up a variety of possibilities for memory-related optimizations of embedded control systems, that will be pursued by researchers working on computer-aided design for CPS.",
keywords = "Embedded control systems, memory analysis, nonuniform sampling, quality of control (QoC)",
author = "Wanli Chang and Dip Goswami and Samarjit Chakraborty and Lei Ju and Jason Xue and Sidharta Andalam",
year = "2016",
month = "9",
day = "27",
doi = "10.1109/TCAD.2016.2613933",
language = "English",
volume = "36",
pages = "586--599",
journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",
number = "4",

}

RIS (suitable for import to EndNote) - Download

TY - JOUR

T1 - Memory-aware embedded control systems design

AU - Chang, Wanli

AU - Goswami, Dip

AU - Chakraborty, Samarjit

AU - Ju, Lei

AU - Xue, Jason

AU - Andalam, Sidharta

PY - 2016/9/27

Y1 - 2016/9/27

N2 - Control applications are often implemented on highly cost-sensitive and resource-constrained embedded platforms, such as microcontrollers with a small on-chip memory. Typically, control algorithms are designed using model-based approaches, where the details of the implementation platform are completely ignored. As a result, optimizations that integrate platform-level characteristics into the control algorithms design are largely missing. With the emergence of cyber-physical systems (CPS)-oriented thinking, there has lately been a strong interest in co-design of control algorithms and their implementation platforms, leading to work on networked control systems and computation-aware control algorithms design. However, there has so far been no work on integrating the characteristics of a memory architecture into the design of control algorithms. In this paper we, for the first time, show that accounting for the impact of on-chip memory (or cache) reuse on the performance of control applications motivates new techniques for control algorithms design. This leads to significant improvement in quality of control for given resource availability, or more efficient implementations of embedded control applications. We believe that this paper opens up a variety of possibilities for memory-related optimizations of embedded control systems, that will be pursued by researchers working on computer-aided design for CPS.

AB - Control applications are often implemented on highly cost-sensitive and resource-constrained embedded platforms, such as microcontrollers with a small on-chip memory. Typically, control algorithms are designed using model-based approaches, where the details of the implementation platform are completely ignored. As a result, optimizations that integrate platform-level characteristics into the control algorithms design are largely missing. With the emergence of cyber-physical systems (CPS)-oriented thinking, there has lately been a strong interest in co-design of control algorithms and their implementation platforms, leading to work on networked control systems and computation-aware control algorithms design. However, there has so far been no work on integrating the characteristics of a memory architecture into the design of control algorithms. In this paper we, for the first time, show that accounting for the impact of on-chip memory (or cache) reuse on the performance of control applications motivates new techniques for control algorithms design. This leads to significant improvement in quality of control for given resource availability, or more efficient implementations of embedded control applications. We believe that this paper opens up a variety of possibilities for memory-related optimizations of embedded control systems, that will be pursued by researchers working on computer-aided design for CPS.

KW - Embedded control systems

KW - memory analysis

KW - nonuniform sampling

KW - quality of control (QoC)

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U2 - 10.1109/TCAD.2016.2613933

DO - 10.1109/TCAD.2016.2613933

M3 - Article

VL - 36

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EP - 599

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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ER -