Meshed Bluetree: Time-Predictable Multi-Memory Interconnect for Multi-Core Architectures

By the same authors

Meshed Bluetree: Time-Predictable Multimemory Interconnect for Multicore Architectures
Wang, H., Audsley, N. C., Hu, X. S. & Chang, W., 2 Oct 2020
Article in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Addressing resource contention and timing predictability for multi-core architectures with shared memory interconnects
Wang, H., Audsley, N. C. & Chang, W., Apr 2020, Proceedings - 2020 IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2020. Institute of Electrical and Electronics Engineers Inc., p. 70-81 12 p. 9113099. (Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS; vol. 2020-April).
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Reliable Resource Sharing on Multiprocessor Mixed-Criticality Systems
Gray, I., Chen, N., Zhao, S., Burns, A. & Chang, W., 29 Jun 2022, IEEE 28th Real-Time and Embedded Technology and Applications Symposium (RTAS).
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
AXI-IC^RT: Towards a Real-Time AXI-Interconnect for Highly Integrated SoCs
Gray, I., Jiang, Z., Yang, K., Fisher, N., Audsley, N. C. & Dong, Z., 31 May 2022
Article in IEEE Transactions on Computers
HIART-MCS: High Resilience and Approximated Computing Architecture for Imprecise Mixed-Criticality Systems
Jiang, Z., Dai, X. & Audsley, N. C., 7 Dec 2021, IEEE Real-Time Systems Symposium. IEEE, p. 290-303
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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reTSN: Resilient and Efficient Time-Sensitive Network for Automotive In-Vehicle Communication
Zou, J., Dai, X. & McDermid, J. A., 12 Jul 2022
Article in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Towards an Analysable, Scalable, Energy-Efficient I/O Virtualization for Mixed-Criticality Systems
Jiang, Z., Dai, X., Dong, P., Wei, R., Yang, D., Audsley, N. & Guan, N., 2021, (Accepted/In press)
Article in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Meshed Bluetree: Time-Predictable Multimemory Interconnect for Multicore Architectures
Wang, H., Audsley, N. C., Hu, X. S. & Chang, W., 2 Oct 2020
Article in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dynamic DAG Scheduling on Multiprocessor Systems: Reliability, Energy and Makespan
Huang, J., Li, R., Jiao, X., Jiang, Y. & Chang, W., 7 Jul 2020, (Accepted/In press)
Article in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
EM-Fuzz: Augmented Firmware Fuzzing via Memory Checking
Gao, J., Xu, Y., Jiang, Y., Liu, Z., Chang, W., Jiao, X. & Sun, J., 7 Jul 2020, (Accepted/In press)
Article in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Research output: Contribution to journal › Article › peer-review

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Author(s)

Haitong Wang
Neil Cameron Audsley
Sharon Hu
Wanli Chang

Department/unit(s)

Computer Science

Publication details

Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Date	Accepted/In press - 7 Jul 2020
Issue number	CODES+ISSS 2020
Original language	English

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Meshed Bluetree: Time-Predictable Multi-Memory Interconnect for Multi-Core Architectures

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