Meshed Bluetree: Time-Predictable Multi-Memory Interconnect for Multi-Core Architectures

By the same authors

Meshed Bluetree: Time-Predictable Multimemory Interconnect for Multicore Architectures
Wang, H., Audsley, N. C., Hu, X. S. & Chang, W., 2 Oct 2020
Article in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Addressing resource contention and timing predictability for multi-core architectures with shared memory interconnects
Wang, H., Audsley, N. C. & Chang, W., Apr 2020, Proceedings - 2020 IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2020. Institute of Electrical and Electronics Engineers Inc., p. 70-81 12 p. 9113099. (Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS; vol. 2020-April).
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Brief Industry Paper: Digital Twin for Dependable Multi-Core Real-Time Systems --- Requirements and Open Challenges
Dai, X., Zhao, S., Bate, I. J., Burns, A., Guo, X. & Chang, W., 16 Mar 2021, (Accepted/In press) IEEE Real-Time and Embedded Technology and Applications Symposium.
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Towards an Analysable, Scalable, Energy-Efficient I/O Virtualization for Mixed-Criticality Systems
Jiang, Z., Dai, X., Dong, P., Wei, R., Yang, D., Audsley, N. & Guan, N., 2021, (Accepted/In press)
Article in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Development Automation of Real-Time Java: Model-Driven Transformation and Synthesis
Chang, W., Wei, R., Zhao, S., Wellings, A., Woodcock, J. & Burns, A., Nov 2020
Article in ACM Transactions on Embedded Computing Systems

From the same journal

Dynamic DAG Scheduling on Multiprocessor Systems: Reliability, Energy and Makespan
Huang, J., Li, R., Jiao, X., Jiang, Y. & Chang, W., 7 Jul 2020, (Accepted/In press)
Article in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
EM-Fuzz: Augmented Firmware Fuzzing via Memory Checking
Gao, J., Xu, Y., Jiang, Y., Liu, Z., Chang, W., Jiao, X. & Sun, J., 7 Jul 2020, (Accepted/In press)
Article in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LEVAX: An Input-Aware Learning-Based Error Model of Voltage-Scaled Functional Units
Jiao, X., Ma, D., Chang, W. & Jiang, Y., 24 Mar 2020, (Accepted/In press)
Article in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Research output: Contribution to journal › Article › peer-review

Full text download(s)

codes20
339 KB, PDF document

Author(s)

Haitong Wang
Neil Cameron Audsley
Sharon Hu
Wanli Chang

Department/unit(s)

Computer Science

Publication details

Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Date	Accepted/In press - 7 Jul 2020
Issue number	CODES+ISSS 2020
Original language	English

Discover related content

Find related publications, people, projects, datasets and more using interactive charts.

View graph of relations

York staff: edit these data

The York Research Database

By the same authors

From the same journal

Meshed Bluetree: Time-Predictable Multi-Memory Interconnect for Multi-Core Architectures

Full text download(s)

Author(s)

Department/unit(s)

Publication details

Discover related content