Monolithic technology for silicon nanowires in high-topography architectures

TY - JOUR

T1 - Monolithic technology for silicon nanowires in high-topography architectures

AU - Nasr Esfahani, M.

AU - Yilmaz, Mustafa

AU - Wollschläger, Nicole

AU - Rangelow, Ivo W.

AU - Leblebici, Yusuf

AU - Alaca, B. Erdem

N1 - Funding Information: The authors gratefully acknowledge the support by Tubitak under Grant no. 112E058. MNE was supported in part by the Swiss Government Excellence Grant. Part of these results has have been obtained in the frame of FP7/2007?2013 under Grant No. 318804 (SNM). The authors would like to acknowledge the help by the CMi Staff. Funding Information: The authors gratefully acknowledge the support by Tubitak under Grant no. 112E058 . MNE was supported in part by the Swiss Government Excellence Grant. Part of these results has have been obtained in the frame of FP7 /2007–2013 under Grant No. 318804 (SNM). The authors would like to acknowledge the help by the CMi Staff. Publisher Copyright: © 2017 Elsevier B.V.

PY - 2017/11/5

Y1 - 2017/11/5

N2 - Integration of silicon nanowires (Si NWs) in three-dimensional (3D) devices including integrated circuits (ICs) and microelectromechanical systems (MEMS) leads to enhanced functionality and performance in diverse applications. The immediate challenge to the extensive use of Si NWs in modern electronic devices is their integration with the higher-order architecture. Topography-related limits of integrating Si NWs in the third dimension are addressed in this work. Utilizing a well-tuned combination of etching and protection processes, Si NWs are batch-produced in bulk Si with an extreme trench depth of 40 μm, the highest trench depth obtained in a monolithic fashion within the same Si crystal so far. The implications of the technique for the thick silicon-on-insulator (SOI) technology are investigated. The process is transferred to SOI wafers yielding Si NWs with a critical dimension of 100 nm along with a trench aspect ratio of 50. Electrical measurements verify the prospect of utilizing such suspended Si NWs spanning deep trenches as versatile active components in ICs and MEMS. Introducing a new monolithic approach to obtaining Si NWs and the surrounding higher-order architecture within the same SOI wafer, this work opens up new possibilities for modern sensors and power efficient ICs.

AB - Integration of silicon nanowires (Si NWs) in three-dimensional (3D) devices including integrated circuits (ICs) and microelectromechanical systems (MEMS) leads to enhanced functionality and performance in diverse applications. The immediate challenge to the extensive use of Si NWs in modern electronic devices is their integration with the higher-order architecture. Topography-related limits of integrating Si NWs in the third dimension are addressed in this work. Utilizing a well-tuned combination of etching and protection processes, Si NWs are batch-produced in bulk Si with an extreme trench depth of 40 μm, the highest trench depth obtained in a monolithic fashion within the same Si crystal so far. The implications of the technique for the thick silicon-on-insulator (SOI) technology are investigated. The process is transferred to SOI wafers yielding Si NWs with a critical dimension of 100 nm along with a trench aspect ratio of 50. Electrical measurements verify the prospect of utilizing such suspended Si NWs spanning deep trenches as versatile active components in ICs and MEMS. Introducing a new monolithic approach to obtaining Si NWs and the surrounding higher-order architecture within the same SOI wafer, this work opens up new possibilities for modern sensors and power efficient ICs.

KW - 3D integrated circuit

KW - 3D integration

KW - Silicon nanowire

KW - Top-down fabrication

KW - Trench isolation

UR - http://www.scopus.com/inward/record.url?scp=85031499719&partnerID=8YFLogxK

U2 - 10.1016/j.mee.2017.10.001

DO - 10.1016/j.mee.2017.10.001

M3 - Article

AN - SCOPUS:85031499719

SN - 0167-9317

VL - 183-184

SP - 42

EP - 47

JO - Microelectronic Engineering

JF - Microelectronic Engineering

ER -