Operating Beyond FPGA Tool Limitations: Nervous Systems for Embedded Runtime Management
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Title of host publication | DATE '21 |
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Date | Accepted/In press - 13 Nov 2020 |
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Date | Published (current) - 2 Feb 2021 |
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Publisher | IEEE |
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Original language | English |
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Fabrication issues throttle VLSI designs with pes- simistic design constraints and speed-grade device binning nec- essary to avoid failure of devices. We propose that a on chip monitoring system (a Nervous System) can reduce this margin by automatically sensing and reacting to failures and environmental changes at runtime. We demonstrate that pessimistic margins in the FPGA tools allow our test circuit to be overclocked by twice the maximum design tool frequency and run at 50 °C above its maximum operating temperature without error. The Configurable Intelligence Array is introduced as a low-overhead intelligence platform and used for a prototype neural circuit that can close the loop between a timing-fault detector and a programmable Phase Locked Loop (PLL) oscillator.
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- FPGA, NERVOUS SYSTEM, runtime management, adaptive systems, dark silicon, FAULT TOLERANCE, Autonomous systems, Bio-inspired Hardware, Social Insect Inspired Systems
Project: Research project (funded) › Research
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