Operating Beyond FPGA Tool Limitations: Nervous Systems for Embedded Runtime Management

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Fabrication issues throttle VLSI designs with pes- simistic design constraints and speed-grade device binning nec- essary to avoid failure of devices. We propose that a on chip monitoring system (a Nervous System) can reduce this margin by automatically sensing and reacting to failures and environmental changes at runtime. We demonstrate that pessimistic margins in the FPGA tools allow our test circuit to be overclocked by twice the maximum design tool frequency and run at 50 °C above its maximum operating temperature without error. The Configurable Intelligence Array is introduced as a low-overhead intelligence platform and used for a prototype neural circuit that can close the loop between a timing-fault detector and a programmable Phase Locked Loop (PLL) oscillator.
Original languageEnglish
Title of host publicationDATE '21
Subtitle of host publicationProceedings of the 24th Conference on Design, Automation and Test in Europe
Publication statusPublished - 2 Feb 2021
EventDesign Automation and Test Europe - Virtual Conference
Duration: 1 Feb 20215 Feb 2021


ConferenceDesign Automation and Test Europe
Abbreviated titleDATE
Internet address

Bibliographical note

This is an author-produced version of the published paper. Uploaded in accordance with the publisher’s self-archiving policy. Further copying may not be permitted; contact the publisher for details.


  • FPGA
  • runtime management
  • adaptive systems
  • dark silicon
  • Autonomous systems
  • Bio-inspired Hardware
  • Social Insect Inspired Systems

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