Operating Beyond FPGA Tool Limitations: Nervous Systems for Embedded Runtime Management

Matthew Rowlings; Andy Tyrrell; Martin Albrecht Trefzer

Operating Beyond FPGA Tool Limitations: Nervous Systems for Embedded Runtime Management

Matthew Rowlings, Andy Tyrrell, Martin Albrecht Trefzer

Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Fabrication issues throttle VLSI designs with pes- simistic design constraints and speed-grade device binning nec- essary to avoid failure of devices. We propose that a on chip monitoring system (a Nervous System) can reduce this margin by automatically sensing and reacting to failures and environmental changes at runtime. We demonstrate that pessimistic margins in the FPGA tools allow our test circuit to be overclocked by twice the maximum design tool frequency and run at 50 °C above its maximum operating temperature without error. The Configurable Intelligence Array is introduced as a low-overhead intelligence platform and used for a prototype neural circuit that can close the loop between a timing-fault detector and a programmable Phase Locked Loop (PLL) oscillator.

Original language	English
Title of host publication	DATE '21
Subtitle of host publication	Proceedings of the 24th Conference on Design, Automation and Test in Europe
Publisher	IEEE
Publication status	Published - 2 Feb 2021
Event	Design Automation and Test Europe - Virtual Conference Duration: 1 Feb 2021 → 5 Feb 2021 https://www.date-conference.com

Conference

Conference	Design Automation and Test Europe
Abbreviated title	DATE
Period	1/02/21 → 5/02/21
Internet address	https://www.date-conference.com

Bibliographical note

This is an author-produced version of the published paper. Uploaded in accordance with the publisher’s self-archiving policy. Further copying may not be permitted; contact the publisher for details.

Keywords

FPGA
NERVOUS SYSTEM
runtime management
adaptive systems
dark silicon
FAULT TOLERANCE
Autonomous systems
Bio-inspired Hardware
Social Insect Inspired Systems

Access to Document

DATE_2021
This is an author-produced version of the published paper. Uploaded in accordance with the publisher’s self-archiving policy. Further copying may not be permitted; contact the publisher for details.
Accepted author manuscript, 5.54 MB

Bio-inspired Adaptive Architectures and Systems
Tyrrell, A., Dunn, K., Tempesti, G., Timmis, J., Trefzer, M. A. & Turner, A. P.
EPSRC
28/02/14 → 31/08/19
Project: Research project (funded) › Research

Cite this

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title = "Operating Beyond FPGA Tool Limitations: Nervous Systems for Embedded Runtime Management",

abstract = "Fabrication issues throttle VLSI designs with pes- simistic design constraints and speed-grade device binning nec- essary to avoid failure of devices. We propose that a on chip monitoring system (a Nervous System) can reduce this margin by automatically sensing and reacting to failures and environmental changes at runtime. We demonstrate that pessimistic margins in the FPGA tools allow our test circuit to be overclocked by twice the maximum design tool frequency and run at 50 °C above its maximum operating temperature without error. The Configurable Intelligence Array is introduced as a low-overhead intelligence platform and used for a prototype neural circuit that can close the loop between a timing-fault detector and a programmable Phase Locked Loop (PLL) oscillator.",

keywords = "FPGA, NERVOUS SYSTEM, runtime management, adaptive systems, dark silicon, FAULT TOLERANCE, Autonomous systems, Bio-inspired Hardware, Social Insect Inspired Systems",

author = "Matthew Rowlings and Andy Tyrrell and Trefzer, {Martin Albrecht}",

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TY - GEN

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AU - Rowlings, Matthew

AU - Tyrrell, Andy

AU - Trefzer, Martin Albrecht

N1 - This is an author-produced version of the published paper. Uploaded in accordance with the publisher’s self-archiving policy. Further copying may not be permitted; contact the publisher for details.

PY - 2021/2/2

Y1 - 2021/2/2

N2 - Fabrication issues throttle VLSI designs with pes- simistic design constraints and speed-grade device binning nec- essary to avoid failure of devices. We propose that a on chip monitoring system (a Nervous System) can reduce this margin by automatically sensing and reacting to failures and environmental changes at runtime. We demonstrate that pessimistic margins in the FPGA tools allow our test circuit to be overclocked by twice the maximum design tool frequency and run at 50 °C above its maximum operating temperature without error. The Configurable Intelligence Array is introduced as a low-overhead intelligence platform and used for a prototype neural circuit that can close the loop between a timing-fault detector and a programmable Phase Locked Loop (PLL) oscillator.

AB - Fabrication issues throttle VLSI designs with pes- simistic design constraints and speed-grade device binning nec- essary to avoid failure of devices. We propose that a on chip monitoring system (a Nervous System) can reduce this margin by automatically sensing and reacting to failures and environmental changes at runtime. We demonstrate that pessimistic margins in the FPGA tools allow our test circuit to be overclocked by twice the maximum design tool frequency and run at 50 °C above its maximum operating temperature without error. The Configurable Intelligence Array is introduced as a low-overhead intelligence platform and used for a prototype neural circuit that can close the loop between a timing-fault detector and a programmable Phase Locked Loop (PLL) oscillator.

KW - FPGA

KW - NERVOUS SYSTEM

KW - runtime management

KW - adaptive systems

KW - dark silicon

KW - FAULT TOLERANCE

KW - Autonomous systems

KW - Bio-inspired Hardware

KW - Social Insect Inspired Systems

M3 - Conference contribution

BT - DATE '21

PB - IEEE

Y2 - 1 February 2021 through 5 February 2021

ER -

Operating Beyond FPGA Tool Limitations: Nervous Systems for Embedded Runtime Management

Abstract

Conference

Bibliographical note

Keywords

Access to Document

Projects

Bio-inspired Adaptive Architectures and Systems

Cite this