Optimising Variability Tolerant Standard Cell Libraries

TY - JOUR

T1 - Optimising Variability Tolerant Standard Cell Libraries

AU - Hilder, James A.

AU - Walker, James Alfred

AU - Tyrrell, Andy M.

PY - 2009

Y1 - 2009

N2 - This paper describes an approach to optimise transistor dimensions within a standard cell library. The goal is to extract high-speed and low-power circuits which are more tolerant to the random fluctuations that will be prevalent in future technology nodes. Using statistically enhanced SPICE models based on 3D-atomistic simulations, a Genetic Algorithm optimises the device widths within a circuit using a multi-objective fitness function. The results show the impact of threshold voltage variation can be reduced by optimising transistor widths, and suggest a similar method could be extended to the optimisation of larger circuits.

AB - This paper describes an approach to optimise transistor dimensions within a standard cell library. The goal is to extract high-speed and low-power circuits which are more tolerant to the random fluctuations that will be prevalent in future technology nodes. Using statistically enhanced SPICE models based on 3D-atomistic simulations, a Genetic Algorithm optimises the device widths within a circuit using a multi-objective fitness function. The results show the impact of threshold voltage variation can be reduced by optimising transistor widths, and suggest a similar method could be extended to the optimisation of larger circuits.

KW - INTEGRATED-CIRCUITS

UR - http://www.scopus.com/inward/record.url?scp=70450145487&partnerID=8YFLogxK

M3 - Article

SP - 2273

EP - 2280

JO - 2009 IEEE CONGRESS ON EVOLUTIONARY COMPUTATION, VOLS 1-5

JF - 2009 IEEE CONGRESS ON EVOLUTIONARY COMPUTATION, VOLS 1-5

ER -