Projects per year
This paper describes an approach to optimise transistor dimensions within a standard cell library. The goal is to extract high-speed and low-power circuits which are more tolerant to the random fluctuations that will be prevalent in future technology nodes. Using statistically enhanced SPICE models based on 3D-atomistic simulations, a Genetic Algorithm optimises the device widths within a circuit using a multi-objective fitness function. The results show the impact of threshold voltage variation can be reduced by optimising transistor widths, and suggest a similar method could be extended to the optimisation of larger circuits.
|Number of pages||8|
|Journal||2009 IEEE CONGRESS ON EVOLUTIONARY COMPUTATION, VOLS 1-5|
|Publication status||Published - 2009|
- 1 Finished
NanoCMOS: Meeting the Design Challenges of ....
Tyrrell, A., Walker, J. A. & Hilder, J. A.
1/10/06 → 30/09/10
Project: Research project (funded) › Research