Overcoming Faults using Evolution on the PAnDA Architecture

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This paper explores the potential for transistor level fault tolerance on a new Programmable Analogue and Digital Array (PAnDA) architecture1. In particular, this architecture features Combinatorial Configurable Analogue Blocks (CCABs) that can implement a number of combinatorial functions similar to FPGAs. In addition, PAnDA allows one to reconfigure features of the underlying analogue layer. In PAnDA-EINS, the functions that the CCAB can implement are predefined through the use of a routing block. This paper is a study of whether removing this routing block and allowing direct control of the transistors provides benefits for fault tolerance. Experiments are conducted in two stages. In the first stage, a logic function is evolved on a CCAB and then optimised using a GA. A fault is then injected into the substrate, breaking the logic function. The second stage of the experiment consists of evolving the logic function again on the faulty substrate. The results of these experiments show that the removal of the routing block from the CCAB is beneficial for fault tolerance.
Original languageEnglish
Title of host publicationProceedings of the IEEE Congress on Evolutionary Computation (CEC)
Publication statusPublished - 2013
EventCongress on Evolutionary Computation (CEC) - Canberra
Duration: 8 Dec 200312 Dec 2003


ConferenceCongress on Evolutionary Computation (CEC)


  • fault-tolerance
  • evolutionary computation
  • PAnDA
  • hardware
  • reconfigurable hardware
  • variability

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