PAnDA: A Reconfigurable Architecture that Adapts to Physical Substrate Variations

TY - JOUR

T1 - PAnDA

T2 - A Reconfigurable Architecture that Adapts to Physical Substrate Variations

AU - Walker, James Alfred

AU - Trefzer, Martin Albrecht

AU - Bale, Simon Jonathan

AU - Tyrrell, Andy

PY - 2013/8

Y1 - 2013/8

N2 - Field programmable gate arrays (FPGAs) are widely used in applications where on-line reconfigurable signal processing isrequired. Speed and function density of FPGAs are increasing as transistor sizes shrink to the nano-scale. As these transistors reducein size intrinsic variability becomes more of a problem and in order to reliably create electronic designs according to specification timeconsumingstatistical simulations become necessary; and even with accurate models and statistical simulation, the fabrication yieldwill decrease as every physical instance of a design behaves differently. This paper describes an adaptive, evolvable architecture thatallows for correction and optimisation of circuits directly in hardware using bio-inspired techniques. Similar to FPGAs, the programmableanalogue and digital array (PAnDA) architecture introduced provides a digital configuration layer for circuit design. Accessing additionalconfiguration options of the underlying analogue layer enables continuous adjustment of circuit characteristics at runtime, whichenables dynamic optimisation of the mapped design’s performance. Moreover, the yield of devices can be improved post-fabricationvia reconfiguration of the analogue layer, which can overcome faults induced due to variability and process defects. Since optimisationgoals are generic, i.e. not restricted to reducing stochastic variability, power consumption or increasing speed, the same mechanismscan also enhance the device’s fault tolerant abilities in the case of component degradation and failures during its life-time or whenexposed to hazardous environments.

AB - Field programmable gate arrays (FPGAs) are widely used in applications where on-line reconfigurable signal processing isrequired. Speed and function density of FPGAs are increasing as transistor sizes shrink to the nano-scale. As these transistors reducein size intrinsic variability becomes more of a problem and in order to reliably create electronic designs according to specification timeconsumingstatistical simulations become necessary; and even with accurate models and statistical simulation, the fabrication yieldwill decrease as every physical instance of a design behaves differently. This paper describes an adaptive, evolvable architecture thatallows for correction and optimisation of circuits directly in hardware using bio-inspired techniques. Similar to FPGAs, the programmableanalogue and digital array (PAnDA) architecture introduced provides a digital configuration layer for circuit design. Accessing additionalconfiguration options of the underlying analogue layer enables continuous adjustment of circuit characteristics at runtime, whichenables dynamic optimisation of the mapped design’s performance. Moreover, the yield of devices can be improved post-fabricationvia reconfiguration of the analogue layer, which can overcome faults induced due to variability and process defects. Since optimisationgoals are generic, i.e. not restricted to reducing stochastic variability, power consumption or increasing speed, the same mechanismscan also enhance the device’s fault tolerant abilities in the case of component degradation and failures during its life-time or whenexposed to hazardous environments.

U2 - 10.1109/TC.2013.59

DO - 10.1109/TC.2013.59

M3 - Article

VL - 62

SP - 1584

EP - 1596

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

SN - 0018-9340

IS - 8

M1 - 6482553

ER -