PAnDA: A Reconfigurable Architecture that Adapts to Physical Substrate Variations

Research output: Contribution to journalArticlepeer-review


Field programmable gate arrays (FPGAs) are widely used in applications where on-line reconfigurable signal processing is
required. Speed and function density of FPGAs are increasing as transistor sizes shrink to the nano-scale. As these transistors reduce
in size intrinsic variability becomes more of a problem and in order to reliably create electronic designs according to specification timeconsuming
statistical simulations become necessary; and even with accurate models and statistical simulation, the fabrication yield
will decrease as every physical instance of a design behaves differently. This paper describes an adaptive, evolvable architecture that
allows for correction and optimisation of circuits directly in hardware using bio-inspired techniques. Similar to FPGAs, the programmable
analogue and digital array (PAnDA) architecture introduced provides a digital configuration layer for circuit design. Accessing additional
configuration options of the underlying analogue layer enables continuous adjustment of circuit characteristics at runtime, which
enables dynamic optimisation of the mapped design’s performance. Moreover, the yield of devices can be improved post-fabrication
via reconfiguration of the analogue layer, which can overcome faults induced due to variability and process defects. Since optimisation
goals are generic, i.e. not restricted to reducing stochastic variability, power consumption or increasing speed, the same mechanisms
can also enhance the device’s fault tolerant abilities in the case of component degradation and failures during its life-time or when
exposed to hazardous environments.
Original languageEnglish
Article number6482553
Pages (from-to)1584-1596
Number of pages13
JournalIEEE Transactions on Computers
Issue number8
Publication statusPublished - Aug 2013

Cite this