Performance Analysis of a 3D Wireless Massively Parallel Computer

Christopher Crispin-Bailey; Amir Mansoor Kamali Sarvestani; James Austin

doi:10.3390/jsan7020018

Performance Analysis of a 3D Wireless Massively Parallel Computer

Christopher Crispin-Bailey, Amir Mansoor Kamali Sarvestani, James Austin

Computer Science

Research output: Contribution to journal › Article › peer-review

Abstract

In previous work, the authors presented a 3D hexagonal wireless direct-interconnect network for a massively parallel computer, with a focus on analysing processor utilisation. In this study, we consider the characteristics of such an architecture in terms of link utilisation and power consumption. We have applied a store-and-forward packet-switching algorithm to both our proposed architecture and a traditional wired 5D direct network (the same as IBM’s Blue Gene). Simulations show that for small and medium-size networks the link utility of the proposed architecture is comparable with (and in some cases even better than) traditional 5D networks. This work demonstrates that there is a potential for wireless processing array concepts to address High-Performance Computing (HPC) challenges whilst alleviating some significant physical construction drawbacks of traditional systems.

Original language	English
Article number	16
Number of pages	20
Journal	Journal of Sensor and Actuator Networks
Volume	7
Issue number	2
DOIs	https://doi.org/10.3390/jsan7020018
Publication status	Published - 19 Apr 2018

Bibliographical note

Keywords

wireless networks
packet-switching
buffer management
on-chip radio communication
parallel computing
interconnect network
link utility
power consumption

Access to Document

10.3390/jsan7020018Licence: CC BY

jsan-07-00018
© 2018 by the authors
Final published version, 3.77 MBLicence: CC BY

http://www.mdpi.com/2224-2708/7/2/18/pdfLicence: CC BY

Cite this

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