Performance Analysis of a 3D Wireless Massively Parallel Computer

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JournalJournal of Sensor and Actuator Networks
DateAccepted/In press - 10 Apr 2018
DatePublished (current) - 19 Apr 2018
Issue number2
Number of pages20
Original languageEnglish


In previous work, the authors presented a 3D hexagonal wireless direct-interconnect network for a massively parallel computer, with a focus on analysing processor utilisation. In this study, we consider the characteristics of such an architecture in terms of link utilisation and power consumption. We have applied a store-and-forward packet-switching algorithm to both our proposed architecture and a traditional wired 5D direct network (the same as IBM’s Blue Gene). Simulations show that for small and medium-size networks the link utility of the proposed architecture is comparable with (and in some cases even better than) traditional 5D networks. This work demonstrates that there is a potential for wireless processing array concepts to address High-Performance Computing (HPC) challenges whilst alleviating some significant physical construction drawbacks of traditional systems.

Bibliographical note

© 2018 by the authors

    Research areas

  • wireless networks, packet-switching, buffer management, on-chip radio communication, parallel computing, interconnect network, link utility, power consumption

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