Performance evaluation of HEVC RCL applications mapped onto NoC-based embedded platforms

Wagner Penny; Daniel Palomino; Marcelo Porto; Bruno Zatt; Leandro Indrusiak

doi:10.1145/3338852.3339868

Performance evaluation of HEVC RCL applications mapped onto NoC-based embedded platforms

Wagner Penny, Daniel Palomino, Marcelo Porto, Bruno Zatt, Leandro Indrusiak

Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Today, several applications running into embedded systems have to fulfill soft or hard timing constraints. Video applications, like the modern High Efficiency Video Coding (HEVC), e.g., most often have soft real-time constraints. However, in specific scenarios, such as in robotic surgeries, the coupling of satellites and so on, harder timing constraints arise, becoming a huge challenge. Although the implementation of such applications in Networks-on-Chip (NoCs) being an alternative to reduce their algorithmic complexity and meet real-time constraints, a performance evaluation of the mapped NoC and the schedulability analysis for a given application are mandatory. In this work we make a performance evaluation of HEVC Residual Coding Loop (RCL) mapped onto a NoC-based embedded platform, considering the encoding of a single 1920x1080 pixels frame. A set of analysis exploring the combination of different NoC sizes and task mapping strategies were performed, showing for the typical and upper-bound workload cases scenarios when the application is schedulable and meets the real-time constraints.

Original language	English
Title of host publication	Proceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019
Publisher	ACM
ISBN (Electronic)	9781450368445
DOIs	https://doi.org/10.1145/3338852.3339868
Publication status	Published - 26 Aug 2019
Event	32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019 - Sao Paulo, Brazil Duration: 26 Aug 2019 → 30 Aug 2019

Publication series

Name	Proceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019

Conference

Conference	32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019
Country/Territory	Brazil
City	Sao Paulo
Period	26/08/19 → 30/08/19

Bibliographical note

© 2019 Association for Computing Machinery. This is an author-produced version of the published paper. Uploaded in accordance with the publisher’s self-archiving policy. Further copying may not be permitted; contact the publisher for details.

Keywords

Embedded systems
HEVC
NoC
Real-time systems

Access to Document

10.1145/3338852.3339868

SBCCI_2019_CR_Penny_et_al
© 2019 Association for Computing Machinery. This is an author-produced version of the published paper. Uploaded in accordance with the publisher’s self-archiving policy. Further copying may not be permitted; contact the publisher for details.
Accepted author manuscript, 2.24 MB

Cite this

Penny, W., Palomino, D., Porto, M., Zatt, B., & Indrusiak, L. (2019). Performance evaluation of HEVC RCL applications mapped onto NoC-based embedded platforms. In Proceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019 Article a7 (Proceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019). ACM. https://doi.org/10.1145/3338852.3339868

@inproceedings{848772402ff24240aa7a50799d9d9865,

title = "Performance evaluation of HEVC RCL applications mapped onto NoC-based embedded platforms",

abstract = "Today, several applications running into embedded systems have to fulfill soft or hard timing constraints. Video applications, like the modern High Efficiency Video Coding (HEVC), e.g., most often have soft real-time constraints. However, in specific scenarios, such as in robotic surgeries, the coupling of satellites and so on, harder timing constraints arise, becoming a huge challenge. Although the implementation of such applications in Networks-on-Chip (NoCs) being an alternative to reduce their algorithmic complexity and meet real-time constraints, a performance evaluation of the mapped NoC and the schedulability analysis for a given application are mandatory. In this work we make a performance evaluation of HEVC Residual Coding Loop (RCL) mapped onto a NoC-based embedded platform, considering the encoding of a single 1920x1080 pixels frame. A set of analysis exploring the combination of different NoC sizes and task mapping strategies were performed, showing for the typical and upper-bound workload cases scenarios when the application is schedulable and meets the real-time constraints.",

keywords = "Embedded systems, HEVC, NoC, Real-time systems",

author = "Wagner Penny and Daniel Palomino and Marcelo Porto and Bruno Zatt and Leandro Indrusiak",

note = "{\textcopyright} 2019 Association for Computing Machinery. This is an author-produced version of the published paper. Uploaded in accordance with the publisher{\textquoteright}s self-archiving policy. Further copying may not be permitted; contact the publisher for details.; 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019 ; Conference date: 26-08-2019 Through 30-08-2019",

year = "2019",

month = aug,

day = "26",

doi = "10.1145/3338852.3339868",

language = "English",

series = "Proceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019",

publisher = "ACM",

booktitle = "Proceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019",

address = "United States",

}

Penny, W, Palomino, D, Porto, M, Zatt, B & Indrusiak, L 2019, Performance evaluation of HEVC RCL applications mapped onto NoC-based embedded platforms. in Proceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019., a7, Proceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019, ACM, 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019, Sao Paulo, Brazil, 26/08/19. https://doi.org/10.1145/3338852.3339868

Performance evaluation of HEVC RCL applications mapped onto NoC-based embedded platforms. / Penny, Wagner; Palomino, Daniel; Porto, Marcelo et al.
Proceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019. ACM, 2019. a7 (Proceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Performance evaluation of HEVC RCL applications mapped onto NoC-based embedded platforms

AU - Penny, Wagner

AU - Palomino, Daniel

AU - Porto, Marcelo

AU - Zatt, Bruno

AU - Indrusiak, Leandro

N1 - © 2019 Association for Computing Machinery. This is an author-produced version of the published paper. Uploaded in accordance with the publisher’s self-archiving policy. Further copying may not be permitted; contact the publisher for details.

PY - 2019/8/26

Y1 - 2019/8/26

N2 - Today, several applications running into embedded systems have to fulfill soft or hard timing constraints. Video applications, like the modern High Efficiency Video Coding (HEVC), e.g., most often have soft real-time constraints. However, in specific scenarios, such as in robotic surgeries, the coupling of satellites and so on, harder timing constraints arise, becoming a huge challenge. Although the implementation of such applications in Networks-on-Chip (NoCs) being an alternative to reduce their algorithmic complexity and meet real-time constraints, a performance evaluation of the mapped NoC and the schedulability analysis for a given application are mandatory. In this work we make a performance evaluation of HEVC Residual Coding Loop (RCL) mapped onto a NoC-based embedded platform, considering the encoding of a single 1920x1080 pixels frame. A set of analysis exploring the combination of different NoC sizes and task mapping strategies were performed, showing for the typical and upper-bound workload cases scenarios when the application is schedulable and meets the real-time constraints.

AB - Today, several applications running into embedded systems have to fulfill soft or hard timing constraints. Video applications, like the modern High Efficiency Video Coding (HEVC), e.g., most often have soft real-time constraints. However, in specific scenarios, such as in robotic surgeries, the coupling of satellites and so on, harder timing constraints arise, becoming a huge challenge. Although the implementation of such applications in Networks-on-Chip (NoCs) being an alternative to reduce their algorithmic complexity and meet real-time constraints, a performance evaluation of the mapped NoC and the schedulability analysis for a given application are mandatory. In this work we make a performance evaluation of HEVC Residual Coding Loop (RCL) mapped onto a NoC-based embedded platform, considering the encoding of a single 1920x1080 pixels frame. A set of analysis exploring the combination of different NoC sizes and task mapping strategies were performed, showing for the typical and upper-bound workload cases scenarios when the application is schedulable and meets the real-time constraints.

KW - Embedded systems

KW - HEVC

KW - NoC

KW - Real-time systems

UR - http://www.scopus.com/inward/record.url?scp=85073408645&partnerID=8YFLogxK

U2 - 10.1145/3338852.3339868

DO - 10.1145/3338852.3339868

M3 - Conference contribution

T3 - Proceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019

BT - Proceedings - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019

PB - ACM

T2 - 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019

Y2 - 26 August 2019 through 30 August 2019

ER -

Performance evaluation of HEVC RCL applications mapped onto NoC-based embedded platforms

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access to Document

Other files and links

Cite this