TY - JOUR
T1 - PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels
AU - Garcia-Ortiz, Alberto
AU - Indrusiak, Leandro S.
AU - Murgan, Tudor
AU - Glesner, Manfred
PY - 2009
Y1 - 2009
N2 - Virtual channels are a common alternative for providing quality-of-service to Networks-on-Chip. A drawback of the approach is the increased power consumption because of the suppression of correlation between consecutive flits. This work proposes an architecture based on low-power coding to overcome the aforementioned problem. The technique requires a minimum overhead, while obtaining a significant power reduction (45% in the average case). Exhaustive experimental simulations are provided to demonstrate the advantages of the proposed architecture.
AB - Virtual channels are a common alternative for providing quality-of-service to Networks-on-Chip. A drawback of the approach is the increased power consumption because of the suppression of correlation between consecutive flits. This work proposes an architecture based on low-power coding to overcome the aforementioned problem. The technique requires a minimum overhead, while obtaining a significant power reduction (45% in the average case). Exhaustive experimental simulations are provided to demonstrate the advantages of the proposed architecture.
UR - http://www.scopus.com/inward/record.url?scp=61649117996&partnerID=8YFLogxK
M3 - Article
SN - 0302-9743
VL - 5349
SP - 219
EP - 228
JO - INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION
JF - INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION
ER -