Power consumption in point-to-point interconnect architectures

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Publication details

Title of host publication15TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS
DatePublished - 2002
Pages155-160
Number of pages6
PublisherIEEE COMPUTER SOC
Place of PublicationLOS ALAMITOS
Original languageEnglish
ISBN (Print)0-7695-1807-9

Abstract

As technology shrinks, the importance of the communication architecture in the overall system performance and power consumption increases dramatically. In this work, a framework is developed to estimate the consumption in point-to-point interconnect structures under different anti-crosstalk techniques and bus encoding schemes. To model the effect of cross coupled capacitances, the spatial correlation between adjacent bus lines is considered. Assuming that the data has a Gaussian distribution, both temporal and spatial transition activities are estimated from the signal world level statistics using a polynomial function of the activity in the most significant bit. Analog simulations have been carried out to show the accuracy of the proposed model.

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