Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip

TY - JOUR

T1 - Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip

AU - Garcia-Ortiz, Alberto

AU - Indrusiak, Leandro S.

PY - 2011

Y1 - 2011

N2 - Low-power coding represents an important technique to reduce consumption in modern interconnect architectures. In the case of Network-on-Chip, and specially if they include virtual channels, the coding techniques require to be effective (large reduction of transition activity) and extremely efficient (reduced hardware resources). This work proposes a coding template called PM with those characteristics. Moreover, it shows with a detailed theoretical analysis and a number of experiments the good characteristics of the approach. Some relevant theoretical results on Exact Probability Coding are also developed in the paper.

AB - Low-power coding represents an important technique to reduce consumption in modern interconnect architectures. In the case of Network-on-Chip, and specially if they include virtual channels, the coding techniques require to be effective (large reduction of transition activity) and extremely efficient (reduced hardware resources). This work proposes a coding template called PM with those characteristics. Moreover, it shows with a detailed theoretical analysis and a number of experiments the good characteristics of the approach. Some relevant theoretical results on Exact Probability Coding are also developed in the paper.

KW - REDUCTION

UR - http://www.scopus.com/inward/record.url?scp=79551554965&partnerID=8YFLogxK

M3 - Article

SN - 0302-9743

VL - 6448

SP - 160

EP - 169

JO - INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION

JF - INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION

ER -