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Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip

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Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip. / Garcia-Ortiz, Alberto; Indrusiak, Leandro S.

In: INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, Vol. 6448, 2011, p. 160-169.

Research output: Contribution to journalArticle

Harvard

Garcia-Ortiz, A & Indrusiak, LS 2011, 'Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip', INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, vol. 6448, pp. 160-169.

APA

Garcia-Ortiz, A., & Indrusiak, L. S. (2011). Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip. INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 6448, 160-169.

Vancouver

Garcia-Ortiz A, Indrusiak LS. Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip. INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION. 2011;6448:160-169.

Author

Garcia-Ortiz, Alberto ; Indrusiak, Leandro S. / Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip. In: INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION. 2011 ; Vol. 6448. pp. 160-169.

Bibtex - Download

@article{097a8f38bd064e32bb352dbc28a3e4b1,
title = "Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip",
abstract = "Low-power coding represents an important technique to reduce consumption in modern interconnect architectures. In the case of Network-on-Chip, and specially if they include virtual channels, the coding techniques require to be effective (large reduction of transition activity) and extremely efficient (reduced hardware resources). This work proposes a coding template called PM with those characteristics. Moreover, it shows with a detailed theoretical analysis and a number of experiments the good characteristics of the approach. Some relevant theoretical results on Exact Probability Coding are also developed in the paper.",
keywords = "REDUCTION",
author = "Alberto Garcia-Ortiz and Indrusiak, {Leandro S.}",
year = "2011",
language = "English",
volume = "6448",
pages = "160--169",
journal = "INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION",
issn = "0302-9743",
publisher = "Springer Verlag",

}

RIS (suitable for import to EndNote) - Download

TY - JOUR

T1 - Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip

AU - Garcia-Ortiz, Alberto

AU - Indrusiak, Leandro S.

PY - 2011

Y1 - 2011

N2 - Low-power coding represents an important technique to reduce consumption in modern interconnect architectures. In the case of Network-on-Chip, and specially if they include virtual channels, the coding techniques require to be effective (large reduction of transition activity) and extremely efficient (reduced hardware resources). This work proposes a coding template called PM with those characteristics. Moreover, it shows with a detailed theoretical analysis and a number of experiments the good characteristics of the approach. Some relevant theoretical results on Exact Probability Coding are also developed in the paper.

AB - Low-power coding represents an important technique to reduce consumption in modern interconnect architectures. In the case of Network-on-Chip, and specially if they include virtual channels, the coding techniques require to be effective (large reduction of transition activity) and extremely efficient (reduced hardware resources). This work proposes a coding template called PM with those characteristics. Moreover, it shows with a detailed theoretical analysis and a number of experiments the good characteristics of the approach. Some relevant theoretical results on Exact Probability Coding are also developed in the paper.

KW - REDUCTION

UR - http://www.scopus.com/inward/record.url?scp=79551554965&partnerID=8YFLogxK

M3 - Article

VL - 6448

SP - 160

EP - 169

JO - INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION

JF - INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION

SN - 0302-9743

ER -