Pre fetching across a shared memory tree within a network-on-chip architecture

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Within Network-on-Chip architectures the sharing of external memory by many CPUs provides a key challenge within the design in order that memory latencies do not dominate overall performance. Within this paper, we propose and evaluate a stream based prefetch unit within a NoC architecture that utilises a separate shared memory tree to provide access to external memory from each CPU tile. The paper shows that prefetching is an appropriate architectural technique within NoCs, enabling better system performance.

Original languageEnglish
Title of host publication2013 International Symposium on System-on-Chip, SoC 2013 - Proceedings
PublisherIEEE Computer Society
Publication statusPublished - 2013
Event2013 15th International Symposium on System-on-Chip, SoC 2013 - Tampere, Finland
Duration: 23 Oct 201324 Oct 2013

Conference

Conference2013 15th International Symposium on System-on-Chip, SoC 2013
Country/TerritoryFinland
CityTampere
Period23/10/1324/10/13

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