Abstract
Within Network-on-Chip architectures the sharing of external memory by many CPUs provides a key challenge within the design in order that memory latencies do not dominate overall performance. Within this paper, we propose and evaluate a stream based prefetch unit within a NoC architecture that utilises a separate shared memory tree to provide access to external memory from each CPU tile. The paper shows that prefetching is an appropriate architectural technique within NoCs, enabling better system performance.
Original language | English |
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Title of host publication | 2013 International Symposium on System-on-Chip, SoC 2013 - Proceedings |
Publisher | IEEE Computer Society |
Publication status | Published - 2013 |
Event | 2013 15th International Symposium on System-on-Chip, SoC 2013 - Tampere, Finland Duration: 23 Oct 2013 → 24 Oct 2013 |
Conference
Conference | 2013 15th International Symposium on System-on-Chip, SoC 2013 |
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Country/Territory | Finland |
City | Tampere |
Period | 23/10/13 → 24/10/13 |