Current approaches to instruction cache analysis for determining worst-case execution time rely on building a mathematical model of the cache that tracks its contents at all points in the program. This requires perfect knowledge of the functional behaviour of the cache and may result in extreme complexity and pessimism if many alternative paths through code sections are possible. To overcome these issues, this paper proposes a new hybrid approach in which information obtained from program traces is used to automate the construction of a model of how the cache is used. The resulting model involves the learning of a Bayesian network that predicts which instructions result in cache misses as a function of previously taken paths. The model can then be utilised to predict cache misses for previously unseen inputs and paths. The accuracy of this learned model is assessed against real benchmarks and an established statistical approach to illustrate its benefits.
|Title of host publication||Proceedings of the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2011)|
|Pages||233 - 242|
|Publication status||Published - 2011|
|Event||17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2011) - Toyama, Japan|
Duration: 29 Aug 2011 → 31 Aug 2011
|Conference||17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2011)|
|Period||29/08/11 → 31/08/11|