Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching

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Publication details

DatePublished - 1 Apr 2008
Original languageEnglish


In this paper, we discuss a real-time on-chip communication service with a priority-based wormhole switching policy. A novel off-line schedulability analysis approach is presented. By evaluating diverse inter-relationships among the traffic-flows, this approach can predict the packet network latency based on two quantifiable different delays: direct interference from higher priority traffic-flows and indirect interference from other higher priority traffic-flows. Due to the inevitable existence of parallel interference, we prove that the general problem of determining the exact schedulability of real-time traffic-flow over the on- chip network is NP-hard. However the results presented do form an upper bound. In addition, an error in a previous published scheduling approach is illustrated and remedied. Utilizing this analysis scheme, we can flexibly evaluate at design time the schedulability of a set of traffic-flows with different QoS requirements on a real-time SoC/NoC communication platform.

    Research areas

  • NoC, QoS, SoC, off-line schedulability analysis approach, on-chip networks, packet network latency, parallel interference, real-time communication analysis, traffic-flows, wormhole switching, network-on-chip, optimisation, quality of service, system-on-chip, telecommunication services, telecommunication switching, telecommunication traffic

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