Response Time Analysis of Synchronous Data Flow Programs on a Many-Core Processor

Hamza Rihani, Matthieu Moy, Claire Maiza, Robert Ian Davis, Sebastian Altmeyer

Research output: Contribution to conferencePaperpeer-review


In this paper we introduce a response time analysis technique for Synchronous Data Flow programs mapped to multiple parallel dependent tasks running on a compute cluster of the Kalray MPPA-256 many-core processor. The analysis we derive computes a set of response times and release dates that respect the constraints in the task dependency graph. We extend the Multicore Response Time Analysis (MRTA) framework by deriving a mathematical model of the multilevel bus arbitration policy used by the MPPA. Further, we refine the analysis to account for the release dates and response times of co-runners, and the use of memory banks. Further improvements to the precision of the analysis were achieved by splitting each task into two sequential phases, with the majority of the memory accesses in the first phase, and a small number of writes in the second phase. Our experimental evaluation focused on an avionics case study. Using measurements from the Kalray MPPA-256 as a basis, we show that the new analysis leads to response times that are a factor of 4.15 smaller for this application, than the default approach of assuming worst-case interference on each memory access.
Original languageEnglish
Publication statusPublished - Oct 2016
Event24th International Conference on Real-Time Networks and Systems (RTNS 2016) - Brest, France
Duration: 18 Oct 201621 Oct 2016


Conference24th International Conference on Real-Time Networks and Systems (RTNS 2016)


  • real-time
  • scheduling
  • many-core
  • response time analysis
  • kalyray
  • mppa-256

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