Response Time Analysis of Synchronous Data Flow Programs on a Many-Core Processor

Research output: Contribution to conferencePaper

Standard

Response Time Analysis of Synchronous Data Flow Programs on a Many-Core Processor. / Rihani, Hamza; Moy, Matthieu; Maiza, Claire; Davis, Robert Ian; Altmeyer, Sebastian.

2016. Paper presented at 24th International Conference on Real-Time Networks and Systems (RTNS 2016) , Brest, France.

Research output: Contribution to conferencePaper

Harvard

Rihani, H, Moy, M, Maiza, C, Davis, RI & Altmeyer, S 2016, 'Response Time Analysis of Synchronous Data Flow Programs on a Many-Core Processor' Paper presented at 24th International Conference on Real-Time Networks and Systems (RTNS 2016) , Brest, France, 18/10/16 - 21/10/16, .

APA

Rihani, H., Moy, M., Maiza, C., Davis, R. I., & Altmeyer, S. (2016). Response Time Analysis of Synchronous Data Flow Programs on a Many-Core Processor. Paper presented at 24th International Conference on Real-Time Networks and Systems (RTNS 2016) , Brest, France.

Vancouver

Rihani H, Moy M, Maiza C, Davis RI, Altmeyer S. Response Time Analysis of Synchronous Data Flow Programs on a Many-Core Processor. 2016. Paper presented at 24th International Conference on Real-Time Networks and Systems (RTNS 2016) , Brest, France.

Author

Rihani, Hamza ; Moy, Matthieu ; Maiza, Claire ; Davis, Robert Ian ; Altmeyer, Sebastian. / Response Time Analysis of Synchronous Data Flow Programs on a Many-Core Processor. Paper presented at 24th International Conference on Real-Time Networks and Systems (RTNS 2016) , Brest, France.

Bibtex - Download

@conference{43f1b40b29e1451e9c9a32ae19542c11,
title = "Response Time Analysis of Synchronous Data Flow Programs on a Many-Core Processor",
abstract = "In this paper we introduce a response time analysis technique for Synchronous Data Flow programs mapped to multiple parallel dependent tasks running on a compute cluster of the Kalray MPPA-256 many-core processor. The analysis we derive computes a set of response times and release dates that respect the constraints in the task dependency graph. We extend the Multicore Response Time Analysis (MRTA) framework by deriving a mathematical model of the multilevel bus arbitration policy used by the MPPA. Further, we refine the analysis to account for the release dates and response times of co-runners, and the use of memory banks. Further improvements to the precision of the analysis were achieved by splitting each task into two sequential phases, with the majority of the memory accesses in the first phase, and a small number of writes in the second phase. Our experimental evaluation focused on an avionics case study. Using measurements from the Kalray MPPA-256 as a basis, we show that the new analysis leads to response times that are a factor of 4.15 smaller for this application, than the default approach of assuming worst-case interference on each memory access.",
keywords = "real-time, scheduling, many-core, response time analysis, kalyray, mppa-256",
author = "Hamza Rihani and Matthieu Moy and Claire Maiza and Davis, {Robert Ian} and Sebastian Altmeyer",
year = "2016",
month = "10",
language = "English",
note = "24th International Conference on Real-Time Networks and Systems (RTNS 2016) ; Conference date: 18-10-2016 Through 21-10-2016",

}

RIS (suitable for import to EndNote) - Download

TY - CONF

T1 - Response Time Analysis of Synchronous Data Flow Programs on a Many-Core Processor

AU - Rihani, Hamza

AU - Moy, Matthieu

AU - Maiza, Claire

AU - Davis, Robert Ian

AU - Altmeyer, Sebastian

PY - 2016/10

Y1 - 2016/10

N2 - In this paper we introduce a response time analysis technique for Synchronous Data Flow programs mapped to multiple parallel dependent tasks running on a compute cluster of the Kalray MPPA-256 many-core processor. The analysis we derive computes a set of response times and release dates that respect the constraints in the task dependency graph. We extend the Multicore Response Time Analysis (MRTA) framework by deriving a mathematical model of the multilevel bus arbitration policy used by the MPPA. Further, we refine the analysis to account for the release dates and response times of co-runners, and the use of memory banks. Further improvements to the precision of the analysis were achieved by splitting each task into two sequential phases, with the majority of the memory accesses in the first phase, and a small number of writes in the second phase. Our experimental evaluation focused on an avionics case study. Using measurements from the Kalray MPPA-256 as a basis, we show that the new analysis leads to response times that are a factor of 4.15 smaller for this application, than the default approach of assuming worst-case interference on each memory access.

AB - In this paper we introduce a response time analysis technique for Synchronous Data Flow programs mapped to multiple parallel dependent tasks running on a compute cluster of the Kalray MPPA-256 many-core processor. The analysis we derive computes a set of response times and release dates that respect the constraints in the task dependency graph. We extend the Multicore Response Time Analysis (MRTA) framework by deriving a mathematical model of the multilevel bus arbitration policy used by the MPPA. Further, we refine the analysis to account for the release dates and response times of co-runners, and the use of memory banks. Further improvements to the precision of the analysis were achieved by splitting each task into two sequential phases, with the majority of the memory accesses in the first phase, and a small number of writes in the second phase. Our experimental evaluation focused on an avionics case study. Using measurements from the Kalray MPPA-256 as a basis, we show that the new analysis leads to response times that are a factor of 4.15 smaller for this application, than the default approach of assuming worst-case interference on each memory access.

KW - real-time

KW - scheduling

KW - many-core

KW - response time analysis

KW - kalyray

KW - mppa-256

UR - https://www-users.cs.york.ac.uk/~robdavis/papers/RTNS2016_mppa.pdf

UR - https://www-users.cs.york.ac.uk/~robdavis/

M3 - Paper

ER -