Selective Surface Metallization of Single Crystal Silicon Nanowires via Stencil Lithography

TY - GEN

T1 - Selective Surface Metallization of Single Crystal Silicon Nanowires via Stencil Lithography

AU - Ali, B.

AU - Karimzadehkhouei, M.

AU - Esfahani, M. N.

AU - Leblebici, Y.

AU - Alaca, B. E.

N1 - Funding Information: *Research supported by TUBITAK under grant numbers 118C155 and 120E347. Publisher Copyright: © 2023 IEEE.

PY - 2023/12/12

Y1 - 2023/12/12

N2 - Surface metallization of Silicon Nanowires (Si NWs) is a critical preparation technology for surface functionalization in biochemical sensing applications. Conventional metallization approaches rely on resist lift-off or non-selective protocols, which can lead to contamination and device damage. This work demonstrates a selective and resist-free surface metallization of suspended Si NW in a 3D device architecture via gold stencil lithography (SL). The approach involves control of the stencil-device gap via a thickness-controlled spacer, fabricated onto the stencil, to characterize and minimize geometrical blurring. The approach also prevents potential stencil-device contact-induced damage to suspended Si NW during SL. A significant improvement in spatial resolution for selective metallization onto NW is achieved compared to the state-of-the-art. Additionally, using the proposed approach with spacer thickness control, miniaturization of the stencil aperture dimensions to nanoscale raises the potential for selective metallization of Si NW down to sub-1 μ m in-plane spatial resolution for highly sensitive biochemical sensor applications.

AB - Surface metallization of Silicon Nanowires (Si NWs) is a critical preparation technology for surface functionalization in biochemical sensing applications. Conventional metallization approaches rely on resist lift-off or non-selective protocols, which can lead to contamination and device damage. This work demonstrates a selective and resist-free surface metallization of suspended Si NW in a 3D device architecture via gold stencil lithography (SL). The approach involves control of the stencil-device gap via a thickness-controlled spacer, fabricated onto the stencil, to characterize and minimize geometrical blurring. The approach also prevents potential stencil-device contact-induced damage to suspended Si NW during SL. A significant improvement in spatial resolution for selective metallization onto NW is achieved compared to the state-of-the-art. Additionally, using the proposed approach with spacer thickness control, miniaturization of the stencil aperture dimensions to nanoscale raises the potential for selective metallization of Si NW down to sub-1 μ m in-plane spatial resolution for highly sensitive biochemical sensor applications.

UR - http://www.scopus.com/inward/record.url?scp=85182018876&partnerID=8YFLogxK

U2 - 10.1109/NMDC57951.2023.10344029

DO - 10.1109/NMDC57951.2023.10344029

M3 - Conference contribution

AN - SCOPUS:85182018876

T3 - 2023 IEEE Nanotechnology Materials and Devices Conference, NMDC 2023

SP - 681

EP - 686

BT - 2023 IEEE Nanotechnology Materials and Devices Conference, NMDC 2023

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 18th IEEE Nanotechnology Materials and Devices Conference, NMDC 2023

Y2 - 22 October 2023 through 25 October 2023

ER -