Stencil lithography for bridging MEMS and NEMS

TY - JOUR

T1 - Stencil lithography for bridging MEMS and NEMS

AU - Ali, Basit

AU - Karimzadehkhouei, Mehrdad

AU - Nasr Esfahani, Mohammad

AU - Leblebici, Yusuf

AU - Alaca, B. Erdem

N1 - Funding Information: This work was supported by the Scientific and Technological Research Council of Turkey [grant No. 118C155 and 120E347 ]. Assistance by S. Zare Pakzad and M. Bostan Shirin of Mechanical Characterization Laboratory is highly appreciated. The authors also acknowledge Mr. Seçkin Akıncı of n 2 STAR-Koç University Nanofabrication and Nanocharacterization Center for Scientific and Technological Advanced Research for his assistance in stencil fabrication and Dr. Barış Yağcı from KUYTAM-Koç University Surface Technologies Research Center regarding microscopic characterization. Publisher Copyright: © 2023 The Authors

PY - 2023/6/1

Y1 - 2023/6/1

N2 - The damage inflicted to silicon nanowires (Si NWs) during the HF vapor etch release poses a challenge to the monolithic integration of Si NWs with higher-order structures, such as microelectromechanical systems (MEMS). This paper reports the development of a stencil lithography-based protection technology that protects Si NWs during prolonged HF vapor release and enables their MEMS integration. Besides, a simplified fabrication flow for the stencil is presented offering ease of patterning of backside features on the nitride membrane. The entire process on Si NW can be performed in a resistless manner. HF vapor etch damage to the Si NWs is characterized, followed by the calibration of the proposed technology steps for Si NW protection. The stencil is fabricated and the developed technology is applied on a Si NW-based multiscale device architecture to protectively coat Si NWs in a localized manner. Protection of Si NW under a prolonged (>3 h) HF vapor etch process has been achieved. Moreover, selective removal of the protection layer around Si NW is demonstrated at the end of the process. The proposed technology also offers access to localized surface modifications on a multiscale device architecture for biological or chemical sensing applications.

AB - The damage inflicted to silicon nanowires (Si NWs) during the HF vapor etch release poses a challenge to the monolithic integration of Si NWs with higher-order structures, such as microelectromechanical systems (MEMS). This paper reports the development of a stencil lithography-based protection technology that protects Si NWs during prolonged HF vapor release and enables their MEMS integration. Besides, a simplified fabrication flow for the stencil is presented offering ease of patterning of backside features on the nitride membrane. The entire process on Si NW can be performed in a resistless manner. HF vapor etch damage to the Si NWs is characterized, followed by the calibration of the proposed technology steps for Si NW protection. The stencil is fabricated and the developed technology is applied on a Si NW-based multiscale device architecture to protectively coat Si NWs in a localized manner. Protection of Si NW under a prolonged (>3 h) HF vapor etch process has been achieved. Moreover, selective removal of the protection layer around Si NW is demonstrated at the end of the process. The proposed technology also offers access to localized surface modifications on a multiscale device architecture for biological or chemical sensing applications.

KW - HF vapor etch

KW - MEMS

KW - NEMS

KW - Si nanowires

KW - Stencil lithography

UR - http://www.scopus.com/inward/record.url?scp=85162207174&partnerID=8YFLogxK

U2 - 10.1016/j.mne.2023.100206

DO - 10.1016/j.mne.2023.100206

M3 - Article

AN - SCOPUS:85162207174

SN - 2590-0072

VL - 19

JO - Micro and Nano Engineering

JF - Micro and Nano Engineering

M1 - 100206

ER -