The Evolution of Standard Cell Libraries for Future Technology Nodes

James Alfred Walker, James Alan Hilder, D Reid, A Asenov, S Roy, C Millar, Andy Tyrrell

Research output: Contribution to journalArticlepeer-review


Evolvable Hardware has been a discipline for over fifteen years. Its application
has ranged from simple circuit design to antenna design. However, research in the field has
often been criticised for not addressing real world problems. Intrinsic variability has been
recognised as one of the major challenges facing the semiconductor industry. This paper
describes an approach that optimises designs within a standard cell library by altering the
transistor dimensions. The proposed approach uses a Multi-objective Genetic Algorithm to
optimise the device widths within a standard cell. The designs are analysed using statistically
enhanced transistor models (based on 3D-atomistic simulations) and statistical SPICE
simulations. The goal is to extract High-speed and low-power designs, which are more tolerant
to the random fluctuations present in current and future technology nodes. The results
show improvements in both the speed and power of the optimised standard cells and that the
impact of threshold voltage variation is reduced.
Original languageEnglish
Pages (from-to)235-256
JournalJournal of Genetic Programming and Evolvable Machine
Issue number3
Publication statusPublished - Sept 2011

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