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The Evolution of Standard Cell Libraries for Future Technology Nodes

Research output: Contribution to journalArticle

Standard

The Evolution of Standard Cell Libraries for Future Technology Nodes. / Walker, James Alfred; Hilder, James Alan; Reid, D; Asenov, A; Roy, S; Millar, C; Tyrrell, Andy.

In: Journal of Genetic Programming and Evolvable Machine, Vol. 12, No. 3, 09.2011, p. 235-256.

Research output: Contribution to journalArticle

Harvard

Walker, JA, Hilder, JA, Reid, D, Asenov, A, Roy, S, Millar, C & Tyrrell, A 2011, 'The Evolution of Standard Cell Libraries for Future Technology Nodes', Journal of Genetic Programming and Evolvable Machine, vol. 12, no. 3, pp. 235-256.

APA

Walker, J. A., Hilder, J. A., Reid, D., Asenov, A., Roy, S., Millar, C., & Tyrrell, A. (2011). The Evolution of Standard Cell Libraries for Future Technology Nodes. Journal of Genetic Programming and Evolvable Machine, 12(3), 235-256.

Vancouver

Walker JA, Hilder JA, Reid D, Asenov A, Roy S, Millar C et al. The Evolution of Standard Cell Libraries for Future Technology Nodes. Journal of Genetic Programming and Evolvable Machine. 2011 Sep;12(3):235-256.

Author

Walker, James Alfred ; Hilder, James Alan ; Reid, D ; Asenov, A ; Roy, S ; Millar, C ; Tyrrell, Andy. / The Evolution of Standard Cell Libraries for Future Technology Nodes. In: Journal of Genetic Programming and Evolvable Machine. 2011 ; Vol. 12, No. 3. pp. 235-256.

Bibtex - Download

@article{d97ff8b68332407c9eaec9c7fce8ae77,
title = "The Evolution of Standard Cell Libraries for Future Technology Nodes",
abstract = "Evolvable Hardware has been a discipline for over fifteen years. Its applicationhas ranged from simple circuit design to antenna design. However, research in the field hasoften been criticised for not addressing real world problems. Intrinsic variability has beenrecognised as one of the major challenges facing the semiconductor industry. This paperdescribes an approach that optimises designs within a standard cell library by altering thetransistor dimensions. The proposed approach uses a Multi-objective Genetic Algorithm tooptimise the device widths within a standard cell. The designs are analysed using statisticallyenhanced transistor models (based on 3D-atomistic simulations) and statistical SPICEsimulations. The goal is to extract High-speed and low-power designs, which are more tolerantto the random fluctuations present in current and future technology nodes. The resultsshow improvements in both the speed and power of the optimised standard cells and that theimpact of threshold voltage variation is reduced.",
author = "Walker, {James Alfred} and Hilder, {James Alan} and D Reid and A Asenov and S Roy and C Millar and Andy Tyrrell",
year = "2011",
month = "9",
language = "English",
volume = "12",
pages = "235--256",
journal = "Journal of Genetic Programming and Evolvable Machine",
issn = "1389-2576",
publisher = "Springer New York",
number = "3",

}

RIS (suitable for import to EndNote) - Download

TY - JOUR

T1 - The Evolution of Standard Cell Libraries for Future Technology Nodes

AU - Walker, James Alfred

AU - Hilder, James Alan

AU - Reid, D

AU - Asenov, A

AU - Roy, S

AU - Millar, C

AU - Tyrrell, Andy

PY - 2011/9

Y1 - 2011/9

N2 - Evolvable Hardware has been a discipline for over fifteen years. Its applicationhas ranged from simple circuit design to antenna design. However, research in the field hasoften been criticised for not addressing real world problems. Intrinsic variability has beenrecognised as one of the major challenges facing the semiconductor industry. This paperdescribes an approach that optimises designs within a standard cell library by altering thetransistor dimensions. The proposed approach uses a Multi-objective Genetic Algorithm tooptimise the device widths within a standard cell. The designs are analysed using statisticallyenhanced transistor models (based on 3D-atomistic simulations) and statistical SPICEsimulations. The goal is to extract High-speed and low-power designs, which are more tolerantto the random fluctuations present in current and future technology nodes. The resultsshow improvements in both the speed and power of the optimised standard cells and that theimpact of threshold voltage variation is reduced.

AB - Evolvable Hardware has been a discipline for over fifteen years. Its applicationhas ranged from simple circuit design to antenna design. However, research in the field hasoften been criticised for not addressing real world problems. Intrinsic variability has beenrecognised as one of the major challenges facing the semiconductor industry. This paperdescribes an approach that optimises designs within a standard cell library by altering thetransistor dimensions. The proposed approach uses a Multi-objective Genetic Algorithm tooptimise the device widths within a standard cell. The designs are analysed using statisticallyenhanced transistor models (based on 3D-atomistic simulations) and statistical SPICEsimulations. The goal is to extract High-speed and low-power designs, which are more tolerantto the random fluctuations present in current and future technology nodes. The resultsshow improvements in both the speed and power of the optimised standard cells and that theimpact of threshold voltage variation is reduced.

M3 - Article

VL - 12

SP - 235

EP - 256

JO - Journal of Genetic Programming and Evolvable Machine

JF - Journal of Genetic Programming and Evolvable Machine

SN - 1389-2576

IS - 3

ER -