The PISA architecture, a Viable platform for the Superscalar Execution of Statically Scheduled Stack Code

Christopher Crispin-Bailey; Soyeb Alli

The PISA architecture, a Viable platform for the Superscalar Execution of Statically Scheduled Stack Code

Computer Science

Research output: Contribution to conference › Paper › peer-review

Abstract

Stack processors offer a level of code density unrivalled
by that of register file-based architectures.
This asset can be attributed directly to the fact
that operands are addressed implicitly in stack programs.
However, this implicit addressing also enforces
a serial execution model in the program and
the full impact of this constraint is only realised
when an attempt is made at building superscalar
implementations of a stack processor. This paper
introduces a new architectural paradigm that tries
to alleviate the impact of this constraint whilst retaining
much of the code compactness of stack processors.

Original language	English
Pages	23-26
Number of pages	4
Publication status	Published - 31 Aug 2005
Event	First ERCIM Workshop on Software-Intensive Dependable Embedded Systems - Porto, Portugal Duration: 30 Aug 2005 → 3 Sept 2005

Conference

Conference	First ERCIM Workshop on Software-Intensive Dependable Embedded Systems
Country/Territory	Portugal
City	Porto
Period	30/08/05 → 3/09/05

Access to Document

http://www.ercim.eu/publication/ws-proceedings/EMB-SYS2005.pdf

Cite this

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title = "The PISA architecture, a Viable platform for the Superscalar Execution of Statically Scheduled Stack Code",

abstract = "Stack processors offer a level of code density unrivalledby that of register file-based architectures.This asset can be attributed directly to the factthat operands are addressed implicitly in stack programs.However, this implicit addressing also enforcesa serial execution model in the program andthe full impact of this constraint is only realisedwhen an attempt is made at building superscalarimplementations of a stack processor. This paperintroduces a new architectural paradigm that triesto alleviate the impact of this constraint whilst retainingmuch of the code compactness of stack processors.",

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N2 - Stack processors offer a level of code density unrivalledby that of register file-based architectures.This asset can be attributed directly to the factthat operands are addressed implicitly in stack programs.However, this implicit addressing also enforcesa serial execution model in the program andthe full impact of this constraint is only realisedwhen an attempt is made at building superscalarimplementations of a stack processor. This paperintroduces a new architectural paradigm that triesto alleviate the impact of this constraint whilst retainingmuch of the code compactness of stack processors.

AB - Stack processors offer a level of code density unrivalledby that of register file-based architectures.This asset can be attributed directly to the factthat operands are addressed implicitly in stack programs.However, this implicit addressing also enforcesa serial execution model in the program andthe full impact of this constraint is only realisedwhen an attempt is made at building superscalarimplementations of a stack processor. This paperintroduces a new architectural paradigm that triesto alleviate the impact of this constraint whilst retainingmuch of the code compactness of stack processors.

M3 - Paper

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EP - 26

T2 - First ERCIM Workshop on Software-Intensive Dependable Embedded Systems

Y2 - 30 August 2005 through 3 September 2005

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