The PISA architecture, a Viable platform for the Superscalar Execution of Statically Scheduled Stack Code

Research output: Contribution to conferencePaperpeer-review


Stack processors offer a level of code density unrivalled
by that of register file-based architectures.
This asset can be attributed directly to the fact
that operands are addressed implicitly in stack programs.
However, this implicit addressing also enforces
a serial execution model in the program and
the full impact of this constraint is only realised
when an attempt is made at building superscalar
implementations of a stack processor. This paper
introduces a new architectural paradigm that tries
to alleviate the impact of this constraint whilst retaining
much of the code compactness of stack processors.
Original languageEnglish
Number of pages4
Publication statusPublished - 31 Aug 2005
EventFirst ERCIM Workshop on Software-Intensive Dependable Embedded Systems - Porto, Portugal
Duration: 30 Aug 20053 Sept 2005


ConferenceFirst ERCIM Workshop on Software-Intensive Dependable Embedded Systems

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