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Time-Predictable Out-of-Order Execution for Hard Real-Time Systems

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Publication details

JournalIEEE Transactions on Computers
DatePublished - Sep 2010
Issue number9
Volume59
Number of pages14
Pages (from-to)1210-1223
Original languageEnglish

Abstract

Superscalar out-of-order CPU designs can achieve higher performance than simpler in-order designs through exploitation of instruction-level parallelism in software. However, these CPU designs are often considered to be unsuitable for hard real-time systems because of the difficulty of guaranteeing the worst-case execution time (WCET) of software. This paper proposes and evaluates modifications for a superscalar out-of-order CPU core to allow instruction-level parallelism to be exploited without sacrificing time predictability and support for WCET analysis. Experiments using the M5 O3 CPU simulator show that WCETs can be two-four times smaller than those obtained using an idealized in-order CPU design, as instruction-level parallelism is exploited without compromising timing safety.

    Research areas

  • M5 03 CPU simulator, WCET analysis, hard real-time systems, instruction level parallelism, software worst case execution time, superscalar out-of-order CPU designs, time predictable out-of-order execution, computer graphic equipment, coprocessors, parallel architectures, parallel programming, real-time systems, software architecture, software metrics

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